arch: arm: cortex_a_r: add Kconfig options for cache segregation
On Arm Cortex R52, cache segregation policy controls the number of L1 I/D cache ways that are allocated to Flash and AXIM interface. Adding Kconfig options for configuring it. Writing to IMP_CSCTRL is only permitted before the caches have been enabled, following a system reset. Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
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3 changed files with 44 additions and 3 deletions
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@ -111,6 +111,32 @@ config CPU_CORTEX_R52
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help
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This option signifies the use of a Cortex-R52 CPU
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config CPU_CORTEX_R52_CACHE_SEGREGATION
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bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM"
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depends on CPU_CORTEX_R52
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help
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Control segregation of L1 I/D-Cache ways between Flash and AXIM.
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Updates to the cache segregation controls are only permitted before the caches
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have ever been enabled, following a system reset, otherwise the update is ignored.
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config CPU_CORTEX_R52_ICACHE_FLASH_WAY
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int "L1 I-Cache Flash way"
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depends on CPU_CORTEX_R52_CACHE_SEGREGATION
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range 0 4
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default 0
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help
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Configure L1 I-Cache ways for Flash interface. Default is reset value, all
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I-Cache ways are allocated for AXIM interface.
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config CPU_CORTEX_R52_DCACHE_FLASH_WAY
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int "L1 D-Cache Flash way"
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depends on CPU_CORTEX_R52_CACHE_SEGREGATION
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range 0 4
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default 0
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help
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Configure L1 D-Cache ways for Flash interface. Default is reset value,
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all D-Cache ways are allocated for AXIM interface.
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if CPU_AARCH32_CORTEX_R
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config ARMV7_R
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@ -56,9 +56,12 @@ SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
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cmp r0, #MODE_HYP
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bne EL1_Reset_Handler
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/* Init HSCTLR see Armv8-R AArch32 architecture profile */
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ldr r0, =(HSCTLR_RES1 | SCTLR_I_BIT | SCTLR_C_BIT)
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mcr p15, 4, r0, c1, c0, 0
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/*
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* The HSCTLR register provides top-level control of system operation in Hyp mode.
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* Since the OS is not running in Hyp mode, and considering the Armv8-R AArch32
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* architecture profile, there's no need to modify HSCTLR configuration unless
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* Fast Interrupts need to be enabled.
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*/
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/* Init HACTLR: Enable EL1 access to all IMP DEF registers */
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ldr r0, =HACTLR_INIT
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@ -200,6 +203,12 @@ EL1_Reset_Handler:
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#endif /* CONFIG_DCLS */
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#if defined(CONFIG_CPU_CORTEX_R52_CACHE_SEGREGATION)
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ldr r0, =IMP_CSCTLR(CONFIG_CPU_CORTEX_R52_ICACHE_FLASH_WAY,
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CONFIG_CPU_CORTEX_R52_DCACHE_FLASH_WAY)
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mcr p15, 1, r0, c9, c1, 0
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#endif
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ldr r0, =arm_cpu_boot_params
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#if CONFIG_MP_MAX_NUM_CPUS > 1
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@ -56,6 +56,12 @@
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#define SCTLR_C_BIT BIT(2)
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#define SCTLR_I_BIT BIT(12)
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/* Armv8-R Cortex-R52 Cache Segregation Control Register */
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#define IMP_CSCTLR_DFLW_SHIFT (0)
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#define IMP_CSCTLR_IFLW_SHIFT (8)
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#define IMP_CSCTLR(iway, dway) ((iway << IMP_CSCTLR_IFLW_SHIFT) | \
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((dway << IMP_CSCTLR_DFLW_SHIFT)))
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/* Hyp System Control Register */
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#define HSCTLR_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(18) | BIT(16) | \
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