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2243 commits

Author SHA1 Message Date
Gerard Marull-Paretas a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
Thomas Stranger 77d2490164 arch: arm: core: aarch32: rename z_NmiHandlerSet
rename the function that sets the handler for the nmi.
It should be namespaced and not camel-case:
z_NmiHandlerSet to z_arm_nmi_set_handler

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2023-04-12 08:59:36 +02:00
Kumar Gala 14d59b3b56 cortex_m: tz_ns.h: Fix compiling with arm-clang
We get the following error when building with arm-clang:

error: non-ASM statement in naked function is not supported
        __TZ_WRAP_FUNC(preface, foo1, postface);
        ^
tests/arch/arm/arm_tz_wrap_func/src/main.c:69:25: note: attribute is here
uint32_t __attribute__((naked)) wrap_foo1(uint32_t arg1, uint32_t arg2,
                        ^
1 error generated.

Remove the do/while wrapper to make this a true naked function.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2023-03-31 08:43:18 -05:00
Manuel Argüelles 98d4faf099 arch: arm: cortex_a_r: implement cache API
Implement cache management APIs for Cortex-A/R AArch32 L1 caches.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-03-29 09:03:37 +02:00
Manuel Argüelles c08fab16cd arch: arm: move cache management sources to cortex_m directory
Current implementation of cache management APIs for ARM only applies to
Cortex-M, so move it to its own directory.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-03-29 09:03:37 +02:00
Ayan Kumar Halder 958dcf98e8 arch: arm: aarch32: Add ability to generate zImage header
The image header is compatible for zImage(32) protocol.

Offset  Value          Description
0x24    0x016F2818     Magic number to identify ARM Linux zImage
0x28    start address  The address the zImage starts at
0x2C    end address    The address the zImage ends at

As Zephyr can be built with a fixed load address, Xen/Uboot can read
the image header and decide where to copy the Zephyr image.

Also, it is to be noted that for AArch32 A/R, the vector table should
be aligned to 0x20 address. Refer ARM DDI 0487I.a ID081822, G8-9815,
G8.2.168, VBAR, Vector Base Address Register :-
Bits[4:0] = RES0.
For AArch32 M (Refer DDI0553B.v ID16122022, D1.2.269, VTOR, Vector Table
Offset Register), Bits [6:0] = RES0.
As zImage header occupies 0x30 bytes, thus it is necessary to align
the vector table base address to 0x80 (which satisfies both VBAR and
VTOR requirements).

Also, it is to be noted that not all the AArch32 M class have VTOR, thus
ARM_ZIMAGE_HEADER header depends on
CPU_AARCH32_CORTEX_R || CPU_AARCH32_CORTEX_A || CPU_CORTEX_M_HAS_VTOR.
The reason being the processors which does not have VBAR or VTOR, needs
to have exception vector table at a fixed address in the beginning of
ROM (Refer the comment in arch/arm/core/aarch32/cortex_m/CMakeLists.txt)
. They cannot support any headers.

Also, the first instruction in zImage header is to branch to the kernel
start address. This is to support booting in situations where the zImage
header need not be parsed.

In case of Arm v8M, the first two entries in the reset vector should be
"Initial value for the main stack pointer on reset" and "Start address
for the reset handler" (Refer Armv8M DDI0553B.vID16122022, B3.30,
Vector tables).
In case of Armv7M (ARM DDI 0403E. ID021621, B1.5.3 The vector table),
the first entry is "SP_main. This is the reset value of the Main stack
pointer.".
Thus when v7M or v8M starts from reset, it expects to see these values
at the default reset vector location.
See the following text from Armv7M (ARM DDI 0403E. ID021621, B1-526)
"On powerup or reset, the processor uses the entry at offset 0 as the
initial value for SP_main..."

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
2023-02-27 17:34:12 +01:00
George Ruinelli b2512d2f53 arm: Add missing include
Add missing include to prevent `'EINVAL' undeclared` when
using `CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT=y`

Signed-off-by: George Ruinelli <caco3@ruinelli.ch>
2023-02-25 07:59:56 -05:00
Peter Mitsis 9d83993db0 arch: arm: Remove unused generated offset symbols
Removes unused generated offset symbols under the ARM architecture.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2023-02-23 16:44:07 +01:00
Kumar Gala 434ca63e2f arch: arm: limit FP16 support to Cortex-A or Cortex-R
FP16 isn't something that is supported on Cortex-M so limit the
Kconfig feature to Cortex-A or Cortex-R.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2023-02-23 08:48:01 +01:00
Andrzej Głąbek 22b17e490b arch: arm: aarch32: Introduce z_arm_on_enter_cpu_idle() hook
Introduce an optional hook to be called when the CPU is made idle.
If needed, this hook can be used to prevent the CPU from actually
entering sleep by skipping the WFE/WFI instruction.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-02-21 15:03:30 +01:00
Jordan Yates a3774fd51a arch: option to generate simplified error codes
Add an option to generate simplified error codes instead of more
specific architecture specific error codes. Enable this by default in
tests to make exception tests more generic across hardware.

Fixes #54053.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2023-01-27 18:09:32 +09:00
Dat Nguyen Duy 50e77c2f9a arch: arm: aarch32: cortex_a_r: disable interrupts before context switching
Ultil now Cortex A/R aarch32 implementation for context
switching expects that interrupts was disabled. This is
true if a context switching happens at thread context.

But if a context switching happens at last action during
interrupt context, this assumption is not true because the
interrupts are still enabled (to allow nesting interrupts).

Disable interrupts at the last interrupt action to ensure
the interrupts are always disabled before context switching
is processed

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2023-01-18 16:22:29 +01:00
Stephanos Ioannidis 4a64bfe351 treewide: Use CONFIG_CPP instead of CONFIG_CPLUSPLUS
This commit updates all in-tree code to use `CONFIG_CPP` instead of
`CONFIG_CPLUSPLUS`, which is now deprecated.

Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
2023-01-13 17:42:55 -05:00
Jordan Yates 35e78c4502 arch: arm: return arm specific fatal error reasons
Return specific fault reasons instead of the generic
`K_ERR_CPU_EXCEPTION`, which provides minimal debugging aid.

Fixes #53093.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2023-01-12 10:01:05 +01:00
Carlo Caione 34e0294652 arm: aarch32: Use proper sys functions for cache mainteinance
This patchset is fixing two things:

1. The proper sys_* functions are used for cache mainteinance
   operations.

2. To check the status of the L1 cache the SCB registers are probed so
   the code is assuming a core architecture cache is present, thus make
   the code conditionally compiled on CONFIG_ARCH_CACHE.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-01-10 18:22:32 -05:00
Piotr Jasiński 7fa0af01cf Kconfig: add config for low-priority debug mon isr
Debug monitor needs to be configured to a low priority in order to be
useful for debugging (to prioritize other interrupts when waiting on a
breakpoint).
Added a config that configures the interrupt this way.

Signed-off-by: Piotr Jasiński <piotr.jasinski@nordicsemi.no>
2022-12-28 12:00:46 +01:00
Piotr Jasiński 1fe4b1eb90 linker: make debug monitor isr symbol weak
It seems that currently it's impossible to create a custom
implementation for debug monitor exception without updating the vector
table (z_arm_debug_monitor maps to fault).
My proposition is to make this symbol weak, so that it can be overriden.

Signed-off-by: Piotr Jasiński <piotr.jasinski@nordicsemi.no>
2022-12-28 12:00:46 +01:00
Duong Vu Nam 84b5d39cb6 arm: aarch32: config static regions with MPU disabled
There is the possibility that when reconfiguring the static regions,
some data that must be accessed is temporarily not accesible due to the
change on the MPU regions configuration. Workaround by disabling MPU
when doing the reconfiguration, same as with dynamic regions, until BR
can be enabled.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Duong Vu Nam 47cce0573e arch: update alignment for Cortex-R52
Cortex-R52 doesn't require power of 2 alignment

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Duong Vu Nam b24f4625f0 arch: support nocache for Cortex-R52
Config NOCACHE_MEMORY depend on ARCH_HAS_NOCACHE_MEMORY_SUPPORT. Enable
ARCH_HAS_NOCACHE_MEMORY_SUPPORT for Cortex-R52 to run NXP S32Z/E with
nocache attibute.

Enable nocache in each driver use it.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Duong Vu Nam ee639b64c3 arch: aarch32: add caches capability to Cortex-R52
Support I/D cache for Cortex-R52 to run with cache on NXP S32Z/E.
Make sure no data is present in the D-Cache before initializing mpu

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
Carlo Caione c96313ec3f arm: cache: Rework cache API
And use the new API.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-01 13:40:56 -05:00
Carlo Caione 189cd1f4a2 cache: Rework cache API
The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.

In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.

In particular this changeset is doing three things:

1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
   `CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`

2. The cache API has been reworked.

3. Comments are added.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-01 13:40:56 -05:00
Wilfred Mallawa 7ac69dc4ca arch/arm/core: fixup typo
Fixup trivial typo.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@gmail.com>
2022-11-27 12:11:44 +01:00
Théophile Ranquet 6d8100424a arm: set low exception vector location
The code in prep_c sets VBAR to relocate vector from 0x0, assuming the
low vector bit in SCTLR to be clear. This isn't the case on all
hardware, so set it explicitly to support those.

Signed-off-by: Théophile Ranquet <theophile.ranquet@gmail.com>
2022-11-23 11:36:26 +01:00
Benjamin Gwin b5fe0f7304 arch: arm: mpu: Add support for disabling the background address map
Arm provides a default address map defining default behaviors for
certain address ranges, which can be overlayed with additional regions
in the MPU. Users may also turn off this background map, so that only
regions explicitly programmed in the MPU are allowed.

This provides a Kconfig so that platforms using a non-standard address
map may disable the background address map and provide their own
explicit MPU regions.

Signed-off-by: Benjamin Gwin <bgwin@google.com>
2022-11-16 11:21:06 +01:00
Andrzej Głąbek 6578b218ca arch: arm: aarch32: cortex_m: fault: Fix SCB->CFSR access helpers
This is a follow-up to commit f400c94adf.

Fix typos in names of introduced macros (*STR -> *SR) and cast their
values to uint32_t to avoid warnings reported for messages formatted
with %x.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-11-11 08:56:18 +00:00
Kumar Gala c778eb2a56 smp: Move arrays to use CONFIG_MP_MAX_NUM_CPUS
Move to use CONFIG_MP_MAX_NUM_CPUS for array size declarations instead
of CONFIG_MP_NUM_CPUS.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-10-17 14:40:12 +09:00
Anas Nashif 3d85ae37b6 arm: add missing includes
Add missing includes that were previously included indirectly.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-11 18:37:53 -04:00
Gerard Marull-Paretas ac63bca423 include: add missing sys_clock.h include
Some headers made use of types defined in sys_clock.h (e.g. k_timeout_t)
without including it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Peter Marheine 5eb75b81f7 arm: rename default RAM region from 'SRAM' to 'RAM'
It's useful for RAMABLE_REGION to have a uniform name when
CODE_DATA_RELOCATION is supported, because otherwise the build system
needs to be aware of how the region name differs between architectures.
Since architectures tend to prefer one of 'SRAM' or 'RAM' for that
region, prefer to use 'RAM' as the more general term.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-10-03 10:09:53 +02:00
Enjia Mai d9206aa29b arch: arm: userspace: fix the incorrect ssf under bad syscall
The parameter ssf of the handler_bad_syscall got null pointer
due to that the R1 does not push into the stack in a right
order on cortex-M0. Adjust the pushing order of stack to make
the ssf being passed correctly.

Fixes #50146.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-09-19 09:17:26 +02:00
Gerard Marull-Paretas 79e6b0e0f6 includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.

The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.

NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-09-05 16:31:47 +02:00
Stephanos Ioannidis 8506979f27 arch: arm: mpu: Fix -Wstringop-overread warning
GCC 12 performs bounds checking on the pointer arguments specified like
an array (e.g. `int arg[]`) and treats such arguments with an empty
length as having the length of 0, resulting in the compiler printing
out `stringop-overread' warning when they are accessed.

This commit corrects any pointer arguments declared using the array
expression to use the pointer expression instead.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-08-25 22:29:28 +09:00
Peter Marheine c30833da3a arch: move CODE_DATA_RELOCATION to top level
Support for CODE_DATA_RELOCATION is not inherently limited to ARM, so
move the Kconfig definition to top-level so it can be used by other
architectures. Since support is opt-in (requiring linker script
support), add a helper symbol enabled by architecture config that gates
whether CODE_DATA_RELOCATION is available instead of listing all
supported systems inline.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-24 10:08:06 +02:00
Carlo Caione e05c4b0a92 s2ram: Deal with system off failure
Some platforms have the possibility to cancel the powering off until the
very latest moment (for example if an IRQ is received). Deal with this
kind of failures.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-08-19 12:10:25 +02:00
Carlo Caione 710e7f24fe arch: arm: Fix cache-related Kconfig symbols
Switch to the new cache-related Kconfig symbols.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-08-18 11:30:49 +00:00
Chris Coleman 443f1cb58c arch: arm: aarch32: cortex_m: fault: Prevent BusFault from HardFault
A Cortex-M BusFault often arises from the execution of a function
pointer that got corrupted.

The Zephyr Cortex-M fault handler de-references the `$pc` in
`z_arm_is_synchronous_svc()` to determine if the fault was due to a
kernel oops (ARCH_EXCEPT). This can cause a BusFault if the pc itself
was corrupt. A BusFault from a HardFault will trigger ARM Cortex-M
"Lockup" preventing the Zephyr fault handler from running to
completion. This in turn, results in no fault handling information
getting dumped by the Zephyr fault handler.

To fix the issue, we can simply set the `CCR.BFHFNMIGN` bit prior to
the instruction address dereference which will cause the processor to
ignore the BusFault and return a value of 0x0 instead of entering
lockup. After the operation is complete, we clear `CCR.BFHFNMIGN` as
it would be unexpected for any other code in the fault handler to
trigger a fault.

The issue can be reproduced programmatically with:

```
  void (*unaligned_func)(void) = (void (*)(void))0x50000001;
  unaligned_func();
```

I bumped into this problem while debugging an issue on the nRF9160DK
(`west build --board nrf9160dk_nrf9160ns`) and confirmed that after
making this change I now see the full fault handler print:

```
[00:00:45.582,214] <err> os: Exception occurred in Secure State
[00:00:45.582,244] <err> os: ***** HARD FAULT *****
[...]
[00:00:45.583,984] <err> os: Current thread: 0x2000d340 (shell_uart)
[00:00:45.829,498] <err> fatal_error: Resetting system
```

Signed-off-by: Chris Coleman <chris@memfault.com>
2022-08-10 11:59:38 +02:00
Joakim Andersson f29c53dabf arch: arm: Allow enabling FPU hard ABI with TF-M
Allow enabling FPU with TF-M with the following limitations:
- Only IPC mode is supported by TF-M.
- Disallow FPU hard ABI when building the NS application, the TF-M build
system does not pass the flags correctly to all dependencies.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-08-10 11:59:19 +02:00
Dat Nguyen Duy 8e55e59c59 arch: introduce config DCLS
Some processors support Dual-redundant Core Lock-step
DCLS) topology but the processor still can be ran in
split-lock mode (by default or changed at flash time).
So, introduce config DCLS that is enabled by default if
config CPU_HAS_DCLS is set, it should be disabled if
processor is used in split-lock mode.

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2022-08-04 12:51:25 +09:00
Hake Huang 2acbf01ff7 arch: arm: call z_early_memset instead memset directly
change to call z_early_memset instead of memset so that we can
relocate memset

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-08-01 18:09:28 +01:00
Manuel Arguelles b64d99091b arm: mpu: dsb after writing to SCTLR on MPU disable
Execute data and instruction sync barriers after writing to SCTLR
to disable the MPU, to ensure the registers are set before
proceeding and that the new changes are seen by the instructions
that follow.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2022-07-26 11:09:42 +00:00
Manuel Arguelles a189e93a44 arm: mpu: dsb after writing to SCTLR on MPU enable
Execute data and instruction sync barriers after writing to SCTLR
to enable the MPU, to ensure the registers are set before
proceeding and that the new changes are seen by the instructions
that follow.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2022-07-26 11:09:42 +00:00
Ryan McClelland 1cf8de4b40 arch: arm: cache: fix undefined references to cmsis
When compiling OpenAMP with Zephyr Cache Management, undefined references
are listed for all functions called with in the cache management

Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
2022-07-25 09:40:32 +02:00
Simon Hein b5522fffbc arch: comply to coding guidelines MISRA C:2012 Rule 14.4
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)

Use `do { ... } while (false)' instead of `do { ... } while (0)'.
Use comparisons with zero instead of implicitly testing integers.
Use comparisons with NULL instead of implicitly testing pointers.
Use comparisons with NUL instead of implicitly testing plain chars.

This commit is a subset of the original auditable-branch commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a

Signed-off-by: Simon Hein <SHein@baumer.com>
2022-07-20 09:28:38 -05:00
Tobias Röhmel 1f7847eaad arch: arm: cortex_r: Use spsr_cxsf instead of spsr_hyp
The use of spsr_hyp is "UNPREDICTABLE" for the ARM Cortex-R52.
Some implements choose to implement the behavior, but it
should not be assumed.
Fixes #47330

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2022-07-18 13:25:26 +00:00
Gerard Marull-Paretas f400c94adf arch: arm: aarch32: cortex_m: fault: use CMSIS CFSR defines
We can use definitions provided by "standard CMSIS" to access
MEMFAULT/BUSFAULT/USGFAULT fields in CFSR.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-07-15 11:51:12 +00:00
Jamie Iles 6868058c03 arch: arm: cache: Add cache maintenance functions
This commit adds icache and dcache maintenance functions
for aarch32.

Signed-off-by: Jamie Iles <quic_jiles@quicinc.com>
Signed-off-by: Dave Aldridge <quic_daldridg@quicinc.com>
2022-07-11 16:03:31 +00:00
Carlo Caione 0ed637a7b6 arch: cortex-m: Enable support for S2RAM
Enable S2RAM for Cortex-M hooking up the provided API functions.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 15:26:26 +02:00
Manuel Arguelles 354254ff2b arch: arm: aarch32: mpu: fix is in region check
Buffer size must be decreased by one when non-zero to calculate the
right end address, and this must be checked for overflows.

Variables for region limit renamed for clarity since they may be
understood as the raw register values.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2022-07-11 11:17:02 +02:00
Julien Massot ddcc5fb28d arch: arm: aarch32: add ARMv8-R MPU support
ARMv8-R aarch32 processor has support for
ARM PMSAv8-32. To add support for ARMv8-R we reuse the
ARMv8-M effort and change access to the different registers
such as rbar, rlar, mair, prselr.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2022-07-11 11:17:02 +02:00
Kevin Townsend 0cc2b37d04 arch: arm: aarch32: Disable FPU with TF-M
Removes the ability to enable the FPU with TF-M -- added in
PR #45906, and which is causing CI failures -- until a more
robust solution can be implemented for FPU support w/TF-M.

Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
2022-07-06 11:53:51 -05:00
Joakim Andersson cb32d8e8e9 modules: tfm: Allow enabling FPU in the application with TF-M enabled
Allow the application to enable the FPU when TF-M has been enabled.
Pass the correct compilation flags according to the TF-M integration
guide.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-06-29 14:45:39 +00:00
Carlo Caione 219d5b5adb arm: vector_table: Automatically place the IRQ vector table
Instead of using a custom linker script, rely on the automatic placement
of the IRQ vector table.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-28 12:29:42 +02:00
Stephanos Ioannidis 0ff1e05486 arch: arm: Migrate to K_KERNEL_STACK_ARRAY_DECLARE
This commit updates all deprecated `K_KERNEL_STACK_ARRAY_EXTERN` macro
usages to use the `K_KERNEL_STACK_ARRAY_DECLARE` macro instead.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-06-20 10:25:52 +02:00
Stephanos Ioannidis 19ba592f07 global: Correct extern K_THREAD_STACK_DEFINE usage
This commit corrects all `extern K_THREAD_STACK_DEFINE` macro usages
to use the `K_THREAD_STACK_DECLARE` macro instead.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-06-20 10:25:52 +02:00
Gerard Marull-Paretas 93ce49e53f arch: arm: aarch32: mpu: remove redundant soc.h usage
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.

This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-05 14:48:40 +02:00
Christoph Coenen b3dfc244ad arch: arm: Add support for multiple zero-latency irq priorities
Add the ability to have multiple irq priority levels which are not
masked by irq_lock() by adding CONFIG_ZERO_LATENCY_LEVELS.

If CONFIG_ZERO_LATENCY_LEVELS is set to a value > 1 then multiple zero
latency irqs are reserved by the kernel (and not only one). The priority
of the zero-latency interrupt can be configured by IRQ_CONNECT.

To be backwards compatible the prio argument in IRQ_CONNECT is still
ignored and the target prio set to zero if CONFIG_ZERO_LATENCY_LEVELS
is 1 (default).

Implements #45276

Signed-off-by: Christoph Coenen <ccoenen@baumer.com>
2022-05-13 08:38:28 -05:00
Mark Holden df6b8c3cc4 coredump: arm: Capture callee registers during k_panic() / k_oops
Ensure callee registers included in coredump.
Push callee registers onto stack and pass as param to
z_do_kernel_oops for CONFIG_ARMV7_M_ARMV8_M_MAINLINE
when CONFIG_EXTRA_EXCEPTION_INFO enabled.

Signed-off-by: Mark Holden <mholden@fb.com>
2022-05-12 19:03:34 -04:00
Jordan Yates d778d5c711 arch: aarch32: improve very early debugging
Debugger plugins use the `z_sys_post_kernel` variable to detect whether
the kernel is currently running, and hence whether any threads exist. As
this is just a standard variable however, after a reset the initial
value of this variable is whatever it was before reset (true) until the
bss section is zeroed halfway through `z_arm_prep_c`. Debuggers are
therefore unable to differentiate between a normally running application
and the very first stages of the boot process.

Clearing this variable as the first action upon reset allows debuggers
to display the correct thread state after the first 3 instructions have
run.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-05-10 18:36:51 +02:00
Gerard Marull-Paretas 4b91c2d79f asm: update files with <zephyr/...> include prefix
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Gerard Marull-Paretas 16811660ee arch: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all arch code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:22 +02:00
Bradley Bolen 88ba97fea4 arch: arm: aarch32: cortex_a_r: Add shared FPU support
This adds lazy floating point context switching.  On svc/irq entrance,
the VFP is disabled and a pointer to the exception stack frame is saved
away.  If the esf pointer is still valid on exception exit, then no
other context used the VFP so the context is still valid and nothing
needs to be restored.  If the esf pointer is NULL on exception exit,
then some other context used the VFP and the floating point context is
restored from the esf.

The undefined instruction handler is responsible for saving away the
floating point context if needed.  If the handler is in the first
irq/svc context and the current thread uses the VFP, then the float
context needs to be saved.  Also, if the handler is in a nested context
and the previous context was using the FVP, save the float context.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Stephanos Ioannidis 80bd814131 arch: arm: cortex_r: Initialise VFP D32 registers for DCLS
This commit updates the Cortex-R reset routine to initialise
(synchronise) the VFP D16-D31 registers when Dual-redundant Core
Lock-step (DCLS) is enabled.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-05-05 12:03:27 +09:00
Bradley Bolen 7f44e28619 arch: arm: aarch32: Create z_arm_floating_point_init() for Cortex-R
This will enable the VFP unit on boot to handle the case where
FPU_SHARING is not enabled.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Bradley Bolen 7c1e399179 arch: arm: aarch32: Create a fpu stack frame
Grouping the FPU registers together will make adding FPU support for
Cortex-A/R easier later.  It provides the ability to get the sizeof and
offsetof FPU registers easier.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Bradley Bolen 3f7162fc07 arch: arm: aarch32: Rearrange exception stack frame
Cortex-A/R use a descending stack frame and the hardware does not help
with the stacking.  This led to some less than desirable workarounds in
the exception code where the basic stack frame was saved twice.
Rearranging the order of the exception stack frame removes that problem
and provides a clearer path to saving CPU context in a fully descending
manner.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Stephanos Ioannidis 5181c61797 arch: arm: Add unified floating-point configuration symbols
This commit adds the unified floating-point configuration symbols for
the ARM architectures.

These configuration symbols allow specification of the floating-point
coprocessors, such as VFP (also known as FP for Cortex-M) and NEON,
for the ARM architectures.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-05-05 12:03:27 +09:00
Keith Packard 1638d4851e arch/arm: Use TPIDRURO on cortex-a too
V7-A also supports TPIDRURO, so go ahead and use that for TLS, enabling
thread local storage for the other ARM architectures.

Add __aeabi_read_tp function in case code was compiled to use that.

Signed-off-by: Keith Packard <keithp@keithp.com>
2022-04-28 11:09:01 +09:00
Nicolas Pitre f61b8b8c16 semihosting: fix inline assembly output dependency
Commit d8f186aa4a ("arch: common: semihost: add semihosting
operations") encapsulated semihosting invocation in a per-arch
semihost_exec() function. There is a fixed register variable declaration
for the return value but this variable is not listed as an output
operand to respective inline assembly segments which is an error.
This is not reported as such by gcc and the generated code is still OK
in those particular instances but this is not guaranteed, and clang
does complain about such cases.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-04-24 19:46:15 +02:00
Jordan Yates d8f186aa4a arch: common: semihost: add semihosting operations
Add an API that utilizes the ARM semihosting mechanism to interact with
the host system when a device is being emulated or run under a debugger.

RISCV is implemented in terms of the ARM implementation, and therefore
the ARM definitions cross enough architectures to be defined 'common'.

Functionality is exposed as a separate API instead of syscall
implementations (`_lseek`, `_open`, etc) due to various quirks with
the ARM mechanisms that means function arguments are not standard.

For more information see:
https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>

impl
2022-04-21 13:04:52 +02:00
Ryan McClelland f7ddcd2713 arch: arm: aarch32: initialize FPSCR to reset value for ARMv8.1
With GCC 11 now supporting low overhead branching in ARMv8.1, ASM "LE"
(loop-end) instructions would trigger an INVSTATE hard-fault after
FPSCR was set to 0. This was due to the FPSCR getting a new field in
ARMv8.1. LTPSIZE is now set to it's reset value of Tail predication not
applied.

Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
2022-04-15 10:33:48 -07:00
Ryan McClelland c5b59282d6 arch: arm: aarch32: add Kconfig for arm cortex-m that implements a cache
The Cache is an optional configuration of both the ARM Cortex-M7 and
Cortex-M55. Previously, it was just checking that it was just an M7
rather than knowing that the CPU actually was built with the cache.

Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
2022-04-14 16:12:03 -05:00
Immo Birnbaum 60ee14db96 arch: arm: aarch32: remove unnecessary "EOF" comments
remove unnecessary EOF comment lines at the end of each file.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-04-14 14:43:52 -05:00
Mark Holden eba9c872b1 coredump: Add callee registers to arm arch block
Add version 2 to coredump arm_arch_block
which includes callee registers

Signed-off-by: Mark Holden <mholden@fb.com>
2022-04-13 13:26:37 -07:00
Mateusz Sierszulski ded324c61d arch: arm: change dependency on CODE_DATA_RELOCATION
This commit changes the CODE_DATA_RELOCATON dependency by
adding CPU_AARCH32_CORTEX_R next to CPU_CORTEX_M.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2022-04-11 10:17:14 +02:00
Bradley Bolen 570c254eda arch: arm: aarch32: ARM_STORE_EXC_RETURN only applies to Cortex-M
Cortex-M code is the only flavor that supports switching between secure
and non-secure state so make sure this kconfig only applies to it.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-04-11 10:16:41 +02:00
Bradley Bolen fd2aab3861 arch: arm: aarch32: Fix when mode offset is defined
Commit a2cfb8431d ("arch: arm: Add code for swapping threads between
secure and non-secure") changed the mode variable in the _thread_arch to
be defined by ARM_STORE_EXC_RETURN or USERSPACE.  The generated offset
define for mode was enabled by FPU_SHARING or USERSPACE.  This broke
Cortex-R with FPU, but with ARM_STORE_EXC_RETURN disabled.  Reconcile
the checks.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-04-11 10:16:41 +02:00
Jimmy Brisson 89d0553ca9 cortex-m: Clear pending mpu fault during mpu fault
This is a strange one: The printing code pushes a floating point
register, and is called during the mpu falt. If the floating point
registers are lazily stacked, this fp push can cause another mpu
fault to be pending during the current mpu fault, and tail chained
without returning to PendSV. Since we're already cleaning up the
fp execption reason, we might as well also clean up thisp pending,
spurious mpu exception.

Signed-off-by: Jimmy Brisson <jimmy.brisson@linaro.org>
2022-04-01 09:16:27 -05:00
Jimmy Brisson 35f9a5d715 cortex-m: Abort pending SVC when a thread is killed
If an SVC was pending during the stack overflow, it will run
after the return of the memory manage fault. To the SVC's misfortune of
the SVC handler, the it's invariant, that PSP point to the
hardware-stacked context is no longer valid. When the user has a
k_sys_fatal_error_handler that tries to kill the thread that caused a
stack overflow, this manifests as the svc reading the memory of whatever
is on the stack after being adjusted by the mem manage fault handler, and
that leads to unending, spurious hard faults, locking up the system.

This patch prevents that.

Signed-off-by: Jimmy Brisson <jimmy.brisson@linaro.org>
2022-04-01 09:16:27 -05:00
Jaxson Han a7a8a64e9c arch32: Fix incorrect exc_exit sequence
The incorrect sequence will cause the thread cannot be aborted in the
ISR context. The following test case failed:
tests/kernel/fatal/exception/kernel.common.stack_sentinel.

The stack sentinel detects the stack overflow as normal during a timer
ISR exit. Note that, currently, the stack overflow detection is behind
the context switch checking, and then the detection will call svc to
raise a fatal error resulting in increasing the nested counter(+1). At
this point, it needs a context switch to finally abort the thread.
However, after the fatal error handling, the program cannot do a context
switch either during the svc exit[1], or during the timer ISR exit[2].

[1] is because the svc context is in an interrupt nested state (the
nested counter is 2).
[2] is because the current point (after svc context pop out) is right
behind the switch checking.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2022-03-21 07:31:29 -04:00
Nazar Kazakov f483b1bc4c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-18 13:24:08 -04:00
Julien Massot 1e538607b8 arch: arm: aarch32: Do not relocate vector table on ARMv8-R
ARMv8-R allows to set the vector table address using VBAR
register, so there is no need to relocate it.

Move away vector_table setting from reset.S and move it to
relocate vector table function as it's done for Cortex-M
CPU.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2022-03-17 15:57:15 -05:00
Nazar Kazakov 9713f0d47c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-14 20:22:24 -04:00
Julien Massot 7a510245c9 arch: arm: cortex_a_r: Add support to start in HYP mode
The ARMv8-R processors always boot into Hyp mode (EL2)

To enter EL1:
Program the HACTLR register because it defaults
to only allowing EL2 accesses. HACTLR controls
whether EL1 can access memory region registers and CPUACTLR.
Program the SPSR before entering EL1.
Other registers default to allowing accesses at EL1 from reset.
Set VBAR to the correct location for the vector table.
Set ELR to point to the entry point of the EL1 code and call ERET.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2022-03-11 10:59:48 +01:00
Julien Massot 59aae63f51 arch: arm: Add support for Cortex-R52
Cortex-R52 is an ARMv8-R processor with AArch32 profile.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2022-03-11 10:59:48 +01:00
Fabio Baltieri cfa0205c6f arm: cortex-m: add an option to trap unaligned access
Cortex-M mainline cores have an option to generate a fault on word and
halfword unaligned access [1], this patch adds a Kconfig option for
enabling the feature.

[1] https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/system-control-block/configuration-and-control-register

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2022-03-10 13:47:41 -05:00
Gerard Marull-Paretas dffaf5375c kconfig: tweak Kconfig prompts
Tweak some Kconfig prompts after the removal of "Enable...".

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-09 15:35:54 +01:00
Gerard Marull-Paretas 95fb0ded6b kconfig: remove Enable from boolean prompts
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:

sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-09 15:35:54 +01:00
Bradley Bolen c0dd594d4d arch: arm: aarch32: Change CPU_CORTEX_R kconfig option
Change the CPU_CORTEX_R kconfig option to CPU_AARCH32_CORTEX_R to
distinguish the armv7 version from the armv8 version of Cortex-R.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-02-23 08:14:15 -06:00
Carles Cufi e83a13aabf kconfig: Rename the TEST_EXTRA stack size option to align with the rest
All stack sizes should end with STACK_SIZE.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2022-02-22 08:23:05 -05:00
Bradley Bolen 48333e612a arch: arm: core: aarch32: Fix Cortex-M userspace regression
This was introduced when trying to fix a previous merge conflict.  It
broke userspace tests on nucleo_l073rz.

Fixes #42627

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-02-10 08:40:45 -05:00
Bradley Bolen 643084de0b arch: arm: core: aarch32: Use cmsis functions
These functions help the code to be more self-documenting.  Use them to
make the code's intent clearer.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-02-08 07:35:43 -05:00
Bradley Bolen 4704f598b8 arch: arm: core: aarch32: Change Cortex-R config check
Replace CONFIG_CPU_CORTEX_R with CONFIG_ARMV7_R since it is clearer with
respect to the difference between v7 and v8 Cortex-R.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-02-08 07:35:43 -05:00
Bradley Bolen 2a357e5dfd arch: arm: core: aarch32: Fix the syscall design for Cortex-R
When calling a syscall, the SVC routine will now elevate the thread to
privileged mode and exit the SVC setting the return address to the
syscall handler.  When the thread is swapped back in, it will be running
z_do_arm_syscall in system mode.  That function will run the syscall
then automatically return the thread to usr mode.

This allows running the syscall in sys mode on a thread so that we can
use syscalls that sleep without doing unnatural things.  The previous
implementation would enable interrupts while still in the SVC call and
do weird things with the nesting count.  An interrupt could happen
during this time when the syscall was still in the exception state, but
the nested count had been decremented too soon.  Correctness of the
nested count is important for future floating point unit work.

The Cortex-R behavior now matches that of Cortex-M.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-02-08 07:35:43 -05:00
Daniel Leung aa20e081d2 arm: remove @return doc for void functions
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-12 16:02:16 -05:00
Sebastian Bøe 1f87642f08 arch: cortex_m: Fix dwt cyccnt assert
Fix the assert that checks for existence of a cycle counter.

The field is named NO CYCCNT, so when it is 1, there is no cycle
counter. But we are asserting the opposite.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2021-12-10 12:27:49 +01:00
Gerard Marull-Paretas 7d1bfb51ae drivers: timer: cortex_m_systick: improve ISR installation
A Cortex-M specific function (sys_clock_isr()) was defined as a weak
function, so in practice it was always available when system clock was
enabled, even if no Cortex-M systick was available. This patch
introduces an auxiliary Kconfig option that, when selected, the ISR
function gets installed. External SysTick drivers can also make use of
this function, thus achieving the same functionality offered today but
in a cleaner way.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-12-04 07:34:53 -05:00
Flavio Ceolin 7dd4297214 pm: Remove unused parameter
The number of ticks on z_pm_save_idle_exit is not used and there is
no need to have it.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-11-17 11:15:49 -05:00
Michel Haber 9d815e5251 timing: use runtime cycles for cortex-m systick
Use sys_clock_hw_cycles_per_sec() instead of
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC to determine clock cycles.

Signed-off-by: Michel Haber <michel-haber@hotmail.com>
2021-11-16 10:43:18 +01:00
Nikolai Kondrashov 533b8c971a arch: arm: aarch32: Fix spelling of "want"
Fix spelling of "want" in a comment in _arch_isr_direct_mp().

Signed-off-by: Nikolai Kondrashov <spbnick@gmail.com>
2021-11-02 10:46:00 +01:00
Immo Birnbaum c6141c49c1 arch: arm: core: aarch32: enable ARMv7-R/Cortex-R code for ARMv7-A/Cortex-A
Modify #ifdefs so that any code that is compiled if CONFIG_ARMV7_R is
set is also compiled if CONFIG_ARMV7_A is set.
Modify #ifdefs so that any code that is compiled if CONFIG_CPU_CORTEX_R
is set is also compiled if CONFIG_CPU_AARCH32_CORTEX_A is set.
Modify source dir inclusion in CMakeLists.txt accordingly.

Brief file descriptions have been updated to include Cortex-A whereever
only Cortex-M and Cortex-R were mentioned so far.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-10-28 15:26:50 +02:00
Immo Birnbaum 70c403c215 arch: arm: core: aarch32: introduce basic ARMv7 MMU support
An initial implementation for memory management using the ARMv7 MMU.
A single L1 translation table for the whole 4 GB address space is al-
ways present, a configurable number of L2 page tables are linked to
the L1 table based on the static memory area configuration at boot
time, or whenever arch_mem_map/arch_mem_unmap are called at run-time.

Currently, a CPU with the Multiprocessor Extensions and execution at
PL1 are always assumed. Userspace-related features or thread stack
guard pages are not yet supported. Neither are LPAE, PXN or TEX re-
mapping. All mappings are currently assigned to the same domain. Re-
garding the permissions model, access permissions are specified using
the AP[2:1] model rather than the older AP[2:0] model, which, accor-
ding to ARM's documentation, is deprecated and should no longer be
used. The newer model adds some complexity when it comes to mapping
pages as unaccessible (the AP[2:1] model doesn't support explicit
specification of "no R, no W" permissions, it's always at least "RO"),
this is accomplished by invalidating the ID bits of the respective
page's PTE.

Includes sources, Kconfig integration, adjusted CMakeLists and the
modified linker command file (proper section alignment!).

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-10-28 15:26:50 +02:00
Immo Birnbaum eac90eeb52 arch: arm: core: aarch32: limit ACTLR register access to Cortex-R
The configuration bits ATCMPCEN, B0TCMPCEN and B1TCMPCEN in the ACTLR
register referenced in the function z_arm_tcm_disable_ecc are only de-
fined for Cortex-R CPUs. For Cortex-A CPUs, those bits are declared
as reserved.

Comp.: https://arm-software.github.io/CMSIS_5/Core_A/html/group__CMSIS__ACTLR.html

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-10-28 15:26:50 +02:00
Immo Birnbaum 85f53376dc arch: arm: core: aarch32: Updated brief file description
Updated brief file description so that it also mentions the aarch32
Cortex-A CPUs.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-10-28 15:26:50 +02:00
Immo Birnbaum 38dc87d4d9 arch: arm: core: aarch32: Add ARMv7-A/Cortex-A(9) related Kconfig items
Add the ARMV7_A, CPU_AARCH32_CORTEX_A and CPU_CORTEX_A9 configuration
items.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-10-28 15:26:50 +02:00
Immo Birnbaum 305550a775 arch: arm: core: aarch32: Updated brief file description
Updated brief file description so that it also mentions the aarch32
Cortex-A CPUs.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2021-10-28 15:26:50 +02:00
Keith Packard 177f95464e arm: Use correct macro for z_interrupt_stacks declaration in stack.h
There are two macros for declaring stack arrays:

K_KERNEL_STACK_ARRAY_DEFINE:

	Defines the array, allocating storage and setting the section name

K_KERNEL_STACK_ARRAY_EXTERN

	Declares the name of a stack array allowing code to reference
	the array which must be defined elsewhere

arch/arm/include/aarch32/cortex_m/stack.h was mis-using
K_KERNEL_STACK_ARRAY_DEFINE to declare z_interrupt_stacks by sticking
'extern' in front of the macro use. However, when this macro also set
the object file section for the symbol, having two of those caused a
conflict in the compiler due to the automatic unique name mechanism used
for sections to allow unused symbols to be discarded during linking.

This patch makes the header use the correct macro.

Signed-off-by: Keith Packard <keithp@keithp.com>
2021-10-21 07:34:56 -04:00
Chris Reed 6d2b91461b arm: cortex-m: initialise ptr_esf in get_esf() in fault.c.
This was producing a -Wsometimes-uninitialized warning.

Signed-off-by: Chris Reed <chris.reed@arm.com>
2021-10-17 10:57:03 -04:00
Kumar Gala a6355cb475 arm: aarch32: mpu: Fix build issue with assert
The assert log of z_priv_stacks_ram_start failed to build due to passing
&z_priv_stacks_ram_start instead of just z_priv_stacks_ram_start.

Fixes #39190

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-10-07 10:53:09 -05:00
Alexandre Bourdiol 23c0e16782 arch: arm: core: aarch32: fix regression introduced with Cortex-R
Regression introduced on ARMV6_M_ARMV8_M_BASELINE by Cortex-R PR #28231
Fixes #38421

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-09-09 19:49:37 -04:00
Stephanos Ioannidis 41fd6e003c arch: arm: aarch32: Add half-precision floating-point configs
This commit adds the half-precision (16-bit) floating-point
configurations to the ARM AArch32 architectures.

Enabling CONFIG_FP16 has the effect of specifying `-mfp16-format`
option (in case of GCC) which allows using the half-precision floating
point types such as `__fp16` and `_Float16`.

Note that this configuration can be used regardless of whether a
hardware FPU is available or supports half-precision operations.

When an FP16-capable FPU is not available, the compiler will
automatically provide the software emulations.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2021-08-30 18:17:47 +02:00
Torsten Rasmussen da926f6855 asm: .eabi_attribute Tag_ABI_align_preserved, 1
Tell armlink that files has ensured proper stack alignment.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-30 08:54:23 -04:00
Torsten Rasmussen 302fd804ce interrupts: safeguard isr_wrapper and isr_install
ld linker will only resolve undefined symbols inside functions that is
actually being called.

However, not all linkers behaves this way. Certain linkers, for example
armlink, resolves all undefined symbols even if during a later stage at
the linking the function will be pruned.

Therefore `ifdef CONFIG_GEN_ISR_TABLES` has been placed to safeguard
functions that will call undefined symbols when CONFIG_GEN_ISR_TABLES=y.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen f57483664b arch: arm: swap_helper.S: safe guarding GTEXT(z_arm_do_syscall)
z_arm_do_syscall is only defined and used when CONFIG_USERSPACE=y.

Defining the symbol z_arm_do_syscall in assembly without a corresponding
implementation is fine for GNU ld as long as the function is not
actively called, but armlink fails to link in such cases.

Safegaurd GTEXT(z_arm_do_syscall) so the symbol is only referenced when
actively used, that is when CONFIG_USERSPACE=y.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen 510d7dbfb6 linker: align _ramfunc_ram/rom_start/size linker symbol names
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.

Generally, start and end symbols uses the following pattern, as:
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end

However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end
Section size symbol:      __foo_size
Section LMA start symbol: __foo_load_start

This commit aligns the symbols for _ramfunc_ram/rom to other symbols and
in such a way they follow consistent pattern which allows for linker
script and scatter file generation.

The symbols are named according to the section name they describe.
Section name is `ramfunc`

The following symbols are aligned in this commit:
-  _ramfunc_ram_start  -> __ramfunc_start
-  _ramfunc_ram_end    -> __ramfunc_end
-  _ramfunc_ram_size   -> __ramfunc_size
-  _ramfunc_rom_start  -> __ramfunc_load_start

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Phil Erwin 78ba3ddbc5 arch: arm: mpu: Put a lock around MPU buffer validate
Related to github #22290.  Getting interrupt during mpu buffer validate
is corrupting index register.  Fix applied to ARC is to disable
interrupts during the buffer validate operation.

Signed-off-by: Phil Erwin <phil.erwin@lexmark.com>
2021-08-17 06:06:33 -04:00
Bradley Bolen 046f93627c arch: arm: cortex_r: Support nested exception detection
Cortex-A/R does not have hardware supported nested interrupts, but it is
easily emulatable using the nesting level stored in the kernel
structure.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-08-17 06:06:33 -04:00
Bradley Bolen 1e153b5091 arch: arm: cortex_r: Add support for recoverable data abort
Add functionality based on Cortex-M that enables recovery from a data
abort using zephyr's exception recovery framework.  If there is a
registered z_exc_handle for a function, then use its fixup address if
that function aborts.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-08-17 06:06:33 -04:00
Bradley Bolen ff1a5e7858 arch: arm: cortex_r: Add ARCH_EXCEPT macro
With the addition of userspace support, Cortex-R needs to use SVC calls
to handle oops exceptions.  Add that support by defining ARCH_EXCEPT to
do a svc call.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-08-17 06:06:33 -04:00
Bradley Bolen 65dcab81d0 arch: arm: cortex_r: Do not use user stack in svc/isr modes
The user thread cannot be trusted so do not use the stack pointer it
passes in.  Use the thread's privilege stack when in privileged modes to
make sure a user thread does not trick the svc/isr handlers into writing
to memory it should not.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-08-17 06:06:33 -04:00
Phil Erwin e0bed3b989 arch: arm: cortex_r: Add MPU and USERSPACE support
Use Cortex-M code as a basis for adding MPU support for the Cortex-R.

Signed-off-by: Phil Erwin <phil.erwin@lexmark.com>
2021-08-17 06:06:33 -04:00
Stephanos Ioannidis 6df8f7e435 arch: arm: cortex_m: Add ARMv8.1-M MVE configs
This commit adds the ARMv8.1-M M-Profile Vector Extension (MVE)
configurations as well as the compiler flags to enable it.

The M-Profile Vector Extension consists of the MVE-I and MVE-F
instruction sets which are integer and floating-point vector
instruction sets, respectively.

The MVE-I instruction set is a superset of the ARM DSP instruction
set (ARMv7E-M) and therefore depends on ARMV8_M_DSP, and the MVE-F
instruction set is a superset of the ARM MVE-I instruction set and
therefore depends on ARMV8_1_M_MVEI.

The SoCs that implement the MVE instruction set should select the
following configurations:

  select ARMV8_M_DSP
  select ARMV8_1_M_MVEI
  select ARMV8_1_M_MVEF (if floating-point MVE is supported)

The GCC compiler flags for the MVE instruction set are specified
through the `-mcpu` flag.

In case of the Cortex-M55 (the only supported processor type for
ARMv8.1-M at the time of writing), the `-mcpu=cortex-m55` flag, by
default, enables all the supported extensions which are DSP, MVE-I and
MVE-F.

The extensions that are not supported can be specified by appending
`+no(ext)` to the `-mcpu=cortex-m55` flag:

  -mcpu=cortex-m55           Cortex-M55 with DSP + MVE-I + MVE-F
  -mcpu=cortex-m55+nomve.fp  Cortex-M55 with DSP + MVE-I
  -mcpu=cortex-m55+nomve     Cortex-M55 with DSP
  -mcpu=cortex-m55+nodsp     Cortex-M55 without any extensions

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2021-08-14 20:29:57 -04:00
Daniel Leung c661765f1d arm: cortex-m: setup TLS pointer before switching to main
The TLS global pointer is only set during context switch.
So for the first switch to main thread, the TLS pointer
is NULL which would cause access violation when trying
to access any thread local variables in main thread.
Fix it by setting it before going into main thread.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-07-30 20:16:47 -04:00
Ioannis Glaropoulos ca5623d288 arm: swap: cleanup an #ifdef statement in swap routine
Cleanup an #ifdef statement in swap_helper.S; use
ARMV6_M_ARMV8_M_BASELINE instead of listing all
Cortex-M baseline implementation variants. This
fixes an issue with Cortex-M23 whose Kconfig
define was not included in the original list.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos f795672743 arm: cortex-m: enhance information dump during HardFault escalation
When inside an escalated HardFault, we would like to get
more information about the reason for this escalation. We
first check if the reason for thise escalation is an SVC,
which occurs within a priority level that does not allow
it to trigger (e.g. fault or another SVC). If this is true
we set the error reason according to the provided argument.

Only when this is not a synchronous SVC that caused the HF,
do we check the other reasons for HF escalation (e.g. a BF
inside a previous BF).

We also add a case for a debug event, to complete going through
the available flags in HFSR.

Finally we ASSERT if we cannot find the reason for the escalation.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos 7930829826 arm: cortex-m: move synchronous SVC assessment in a separate function
Move the assessment of a synchronous SVC error into a
separate function. This commit does not introduce any
behavioral changes.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos a8d6c14d30 arm: cortex-m: clean up some more hard-coded constants in swap_helper
Clean up a few more hard-coded constants
in swap_helper.S and replace them with
CMSIS-like defines in cpu.h. No behavioral
changes in this commit.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos 03c4bcd920 arm: use BASEPRI_MAX instead of BASEPRI to mask interrupts
When locking interrupt in a critical session, it is
safer to do MSR BASEPRI_MAX instead of BASEPRI. The
rationale is that when writing to BASEPRI_MAX, the
writing is conditional, and is only applied if the
change is to a higher priority level. This commit
replaces BASEPRI with BASEPRI_MAX in operations that
aim to lock some specific interrupts:
- irq_lock()
- masking out PendSV
So, for example, it is not possible to actually
unmask any interrupts by doing an irq_lock operation.
The commit does not introduce behavioral changes.
However, it makes irq_lock() more robust against
future changes to the IRQ locking mechanism.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos 7156183985 arm: fix the VTOR alignment requirement for Baseline Cortex-M
Baseline Cortex-M requires VTOR to be aligned on 64-word
boundary. That is because bit-7 of VTOR is also RAZ/WI.
The commit updates the vector table section alignment for
Baseline Cortex-M to reflect the implementation constraint.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos ebcd5de596 arm: cortex_a_r: rename z_platform_init to z_arm_platform_init
Platform specific initialization during early boot
has been a feature supported only by Cortex-M; the
Kconfig symbol is define in arch/arm Kconfig space.
We rename the z_platform_init() function to
z_arm_platform_init(), to indicate more clearly that
this is an internal, private ARM-only API.

This commit does not introduce behavioral changes.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos 1706b4dfaa arm: rename z_platform_init to z_arm_platform_init
Platform specific initialization during early boot
has been a feature supported only by Cortex-M; the
Kconfig symbol is defined in arch/arm Kconfig space.
We rename the z_platform_init() function to
z_arm_platform_init(), to indicate more clearly that
this is an internal, private ARM-only API.

This commit does not introduce behavioral changes.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos 70984a1587 arm: set DebugMonitor IRQ unconditionally during initialization
If the DebugMonitor extension is implemented by the core,
the interrupt may be pended and become active, even if it
is not enabled. Set the priority level of DebugMonitor upon
system initialization to the intended value unconditionally
so we do not end up in undefined behavior, if the exception
is accidentally pended. Since the priority level is set at
init, we can remove resetting the priority in DWT driver
initialization.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos 6981b84550 arm: ensure SysTick IRQ level is set unconditionally
When the SoC implements SysTick, but the system
does not use it as the driver for system timing
we still need to set its interrupt level. This
is because the SysTick IRQ is always enabled,
so we must ensure the interrupt priority is set
to a level lower than the kernel interrupts (for
the assert mechanism to work properly) in case
the SysTick interrupt is accidentaly raised.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos 28a59f67b9 arm: route PendSV to spurious IRQ handler if it is unused
If the PendSV interrupt is not used by Zephyr (this is
the case when we build with single-thread support) we
route the interrupt to z_arm_exc_spurious, instead of
assigning 0 to the vector table entry. This is because
the interrupt is always enabled and always exists, so
it is safer to always get the proper error report, in
case we accidentally pend the PendSV, for any reason.

We also add a comment in the PendSV priority setting,
explaining why it has to be assigned a priority level
even if it is not used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Ioannis Glaropoulos 41d3d38aec arm: aarch32: sort the source files lists alphabetically
Re-organize the library sources list so the files
are sorted alphabetically.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-07-28 21:08:18 -04:00
Bradley Bolen 379bb70728 arch: aarch32: cortex_m/r: Add arch exception helper
Create z_arm_preempted_thread_in_user_mode to abstract the
implementation differences between Cortex-M and R to determine if an
exception came from userspace.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-07-28 21:08:09 -04:00
Bradley Bolen 50a6dafdc5 arch: aarch32: cortex_m/r: Add arch helper function
Create z_arm_thread_is_user_mode to abstract the implementation
differences between Cortex-M and R to determine if the current thread is
in user or kernel mode.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-07-28 21:08:09 -04:00
Jeremy Bettis 2de4a902de cmake: Support coverage flags on all archs
Most arch's CMakeLists.txt contain rules to add compiler and linker
flags for coverage if CONFIG_COVERAGE is enabled, but 4 of them were
missing this.

Instead, set the coverage flags in arch/common/CMakeLists.txt which
affects all archs.

Signed-off-by: Jeremy Bettis <jbettis@chromium.org>
2021-06-10 18:01:36 -04:00
Øyvind Rønningstad 382bbacb0a tfm: Put saving of FPU context into its own file so it can be reused
Also, this eases readability.

The new API can be used any time all FP registers must be manually
saved and restored for an operation.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2021-06-07 15:23:22 +02:00
Bradley Bolen 131af7648f arch: arm: cortex_r: Use assembler macros for exceptions
Most of the code for the three exception functions is identical so use
macros to make things easier to read.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-06-04 16:18:01 -05:00
Bradley Bolen 90e76bd891 arch: arm: cortex_r: Use macro for svc call
Use the context switch macro for z_arm_cortex_r_svc to be more clear
about the svc call being executed.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-06-04 16:18:01 -05:00
Henrik Brix Andersen 2b0a481291 arch: arm: cortex-m: add support for clearing NXP MPU regions at boot
Clear NXP MPU regions at boot if CONFIG_INIT_ARCH_HW_AT_BOOT is
enabled.

Fixes: #34045

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-05-26 18:14:03 -05:00
Ioannis Glaropoulos b3b36f69a6 arm: cortex-m: shrink hidden option for null-pointer detection
Shrink the name of the hidden cortex-m option for the
null-pointer dereference detection feature.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-26 12:30:05 -05:00
Ioannis Glaropoulos d105a2b76c arm: shrink names for null-pointer exception detection Kconfigs
Reduce the length of the Kconfig defines related to
null-pointed dereference detection in Cortex-M.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-26 12:30:05 -05:00
Ioannis Glaropoulos 4084242a71 kernel: make MULTITHREADING promptless if single-thread not supported
If single thread builds are not supported by the
architecture, the MULTITHREADING option should be
prompt-less to block any modifications to it. We
also introduce an explicit ARCH-level Kconfig that
reflects whether the ARCH is capable of single-thread
Zephyr builds.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-05-26 11:03:22 -05:00
Aurelien Jarno be49df628f arch: arm: cortex_m: z_arm_mpu_init: fix D-Cache invalidation
In case CONFIG_NOCACHE_MEMORY=y, the D-Cache need to be clean and
invalidated before enabling the MPU to make sure no data from a
__nocache__ region is present in the D-Cache.

If the D-Cache is disabled, SCB_CleanInvalidateDCache() shall not be
used as it might contains random data for random addresses, and this
might just create a bus fault.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2021-05-18 11:39:26 -05:00
Aurelien Jarno 1a583e44ba arch: arm: cortex_m: fix D-Cache reset with CONFIG_INIT_ARCH_HW_AT_BOOT
On reset we do not know what is the status of the D-Cache, nor its
content.

If it is disabled, do not try to clean it, as it might contains random
data for random addresses, and this might just create a bus fault.
Invalidating it is enough.

If it is enabled, it means its content is not random.
SCB_InvalidateDCache() will clean it, invalidate it and disable it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2021-05-18 11:39:26 -05:00
Bradley Bolen 95a7e71661 arch: arm: aarch32: Move mpu code up a level
Move the mpu code to the common aarch32 directory in preparation for
Cortex-R mpu support

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-05-06 19:39:09 +02:00
Gerard Marull-Paretas 280ca7a632 arch: replace power/power.h with pm/pm.h
Replace old header with the new one.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-05-05 18:35:49 -04:00