Enable monolithic build for all BLE apps.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Fix linker error caused by the smartbond timer driver
being enabled at the same time as the smartbond timer counter
driver. For some reason putting SMARTBOND_TIMER=n in a conf
file does not fix this, this change has to be made to the
Kconfig.defconfig to not add this default y case in order
to fix the error. At least that is all I could figure out,
and not sure why the .conf doesn't override it.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Created `GEN_OFFSET_STRUCT` & `GEN_NAMED_OFFSET_STRUCT` that
works for `struct`, and remove the use of `z_arch_esf_t`
completely.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The CLIC requires that mtvec.base is aligned to 64 bytes.
_isr_wrapper is used as mtvec.base, so align it to 64 bytes.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
headers for dmic are now part of the SoC and maintained per generation,
so create one header for PTL and build the code for PTL in some of the
drivers (dmic_nhlt).
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds definition of ACE 3.0 Panther Lake board.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
power_down() expects a cached pointer. Fix the sparse annotation
to match the implementation (sys_cache_cached_ptr_get() returns a cached
pointer so this is correct).
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit introduces support for an alternate linking method in the
LLEXT subsystem, called "SLID" (short for Symbol Link Identifier),
enabled by the CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID Kconfig option.
SLID-based linking uses a unique identifier (integer) to identify
exported symbols, instead of using the symbol name as done currently.
This approach provides several benefits:
* linking is faster because the comparison operation to determine
whether we found the correct symbol in the export table is now an
integer compare, instead of a string compare
* binary size is reduced as symbol names can be dropped from the binary
* confidentiality is improved as a side-effect, as symbol names are no
longer present in the binary
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Select the newly introduced nrf54lx compatible kconfig
option.
This is common both for real HW and for simulated HW,
allowing SW to behave appropriately for both.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This is a soc/board integration for the MediaTek Audio DSP device on
the MT8195 SOC, along with a Zephyr mtk_adsp soc integration that will
work to support similar 8186 and 8188 device shortly.
A python loader (similar to cavsload.py) is included that will run in
developer mode on current chromebooks (an HP x360 13b-ca000 was
tested) with an unmodified kernel.
Signed-off-by: Andy Ross <andyross@google.com>
Create a pseudo-terminal to access Zephyr shell on the audio DSP.
The shell terminal is enabled with "-p" command-line option.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Add a new shell backend implemented over a shared memory window
on the Intel audio DSPs. The implementation uses the Zephyr winstream
to manage the data streaming.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
STM32 MCU shall set voltage regulator level with respect to set clock
frequency to reach optimal power consumption.
Voltage regulator is set prior to clock setting based on configuration
from dts/overlay file. Config_regulator_voltage is set as weak in
clock_stm32_ll_common - config_regulator_voltage can be
extended to other STM32 families without need to rewrite heavily
family clock driver, default one can be still used.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Configure CAN120 MCAN core registers as non-cachable to prevent D-Cache
from inhibiting volatile accesses to the CAN120 MCAN registers. Also
apply non-cachable attribute to the message ram region. Even though the
MCAN driver handles cache invalidation/flushing, MPU faults are still
triggered (to be investigated).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Cosmetic change to align code style when initializing DSP registers. The
code in intel_is_ace() branch was moved as-is from acetool.py when the
two tools were merged to make reviewing easier. Fix the code style to be
coherent in the merged cavstool.py. No functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Use the correct register to read ROM status on intel_adsp_ace20.
Without this this fix, firmware load is successful but
boot takes extra 2 seconds and following warning was emitted:
WARNING:cavs-fw:Load failed? ROM_STATUS = 0x0
The log-only mode (-l) was not working at all and is fixed
by this commit.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This adds support for the local APIC in one-shot mode as the timeout
event source for those cases where the CPU supports invariant TSC but
no TSC deadline capability. It is presented as another timer choice.
Existing Kconfig symbols were preserved to minimize board config
disturbance.
This hybrid approach was implemented kind of backward in the apic_timer
driver but it is far cleaner to carry this here.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Added ADI MAX series soc, first partnumber is MAX32690
The family structure will be
ADI_MAX
MAX32xxx
MAX32655
MAX32655EVKIT
MAX32655FTHR
MAX32666
MAX32666FTHR
MAX32666FTHR2
MAX32690
MAX32690EVKIT
MAX78xxx
MAX78000
MAX78002
...
When MAX32 MCUs goes to sleep mode debugger could not access it
and flashing fails, ARM_ON_ENTER_CPU_IDLE_HOOK prevent
the CPU from actually entering sleep
by skipping the WFE/WFI instruction.
Due to ARM_ON_ENTER_CPU_IDLE_HOOK is not configurable at the user
space, added a config wrapper as MAX32_ON_ENTER_CPU_IDLE_HOOK.
If MAX32_ON_ENTER_CPU_IDLE_HOOK config being defined (default y)
devicei will not goes to sleep mode in idle state.
To disable it add below line in your configuration file
CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK=n
MAX32690 has two core Cortex-M4 and Risc-V this commit adds M4 core
support.
Co-authored-by: Jason Murphy <jason.murphy@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The software protocol to write status value of 0x05 (FW_ENTERED)
into memory window 0 at Zephyr boot, is not needed in the ace1.x
boot flow and does not match the semantics host systems are expecting
at this location in the memory window (e.g. write of 0x05 is not
expected).
Make this logic specific to intel_adsp_cavs platforms and move the code
out from common intel_adsp code.
This commit depends on update to cavstool.py to use correct
ROM status register to observe boot state.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Starting with ace1.x, the boot status is no longer reported by
the boot ROM in the SRAM status window as it was done in older
platforms. The current cavstool.py code works on these newer platforms,
as Zephyr soc bootcode writes to same location, but this is not
the recommended boot flow.
Modify boot flow to use a dedicated register to observe boot
state. This change improves usability of cavstool.py on ace1.x
platforms as:
- it is possible to start cavstool.py (e.g. in log-only or shell mode)
while DSP has been already been booted, but is currently in
low-power mode (and SRAM window is not accessible from host)
- more reliable boot and better error reporting as actual ROM
status is observed
Furthermore, this change allows to remove the memory window
writes from Zephyr intel_adsp boot_complete(). This IPC interface
is application and IPC revision specific and the write should not
be done in generic Zephyr SoC code. However, to keep cavstool.py
working, the tool has to be updated first.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit defines the bt-hci subnode under the bleif node on
Ambiq Apollo3 Blue and Apollo3 Blue Plus SOC.
Also add the default configurations for Bluetooth feature on Ambiq
apollo3_evb and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Clock must be restored as soon as the SoC leaves standby.
Keep the logic inside the SoC instead of delegate it to the pm
subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
clocks instead of just one or the other
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.
Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
k_sem_init() is called for every IPC message sent in
intel_adsp_ipc_send_message(). This has not had any side-effects
in upstream configurations, but has been linked to a failing
run of test_obj_tracking_sanity test case in downstream Zephyr
use.
Replace k_sem_init() with k_sem_reset() as this is more appropriate
API to reset the semaphore count, and ensure deterministic
behaviour in case a thread is waiting on the semaphore at time
of reset.
Suggested-by: Peter Mitsis <peter.mitsis@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Adding supporting soc files for the ke1xz platforms
updating soc.yaml and kinetis soc files
to support ke1xz.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Pavel Krenek <pavel.krenek@nxp.com>
Remove all the hard-configured absolute addresses and zillions of tiny
ELF segments in favor of the auto-generated vector region, which is
guaranteed correct as long as core-isa.h is matched to the target.
Signed-off-by: Andy Ross <andyross@google.com>
Add header file for flash configuration blocks
which is an image header consumed by the RW bootrom.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add new Microchip MEC chips using the new MEC5 HAL and
add a HAL version of a legacy chip named MECH172x.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Corrected virtual memory size to match the range supported by the
Translation Lookup Buffer. The TLB size is 16 MB, however the first 128 KB
is dedicated to LPSRAM and bypasses the TLB. This was taken into account in
KERNEL_VM_BASE, so KERNEL_VM_SIZE was reduced accordingly.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The script runs as part of the build now. Use that feature and
remove the old static file from the manually-run script.
Signed-off-by: Andy Ross <andyross@google.com>
Merge codebases of cavstool.py and acetool.py as the two have
a lot of duplicated code.
To ease with transition, keep acetool.py around with implementation
imported from cavstool.py. This will help to keep any automated
testing flows working that assume both tools exist.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The nRF54H20 EXMIF peripheral requires word accesses. Doing accesses of
byte or half-word sizes results in bus fault.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
RC32K and RCX low power clocks require runtime calibration to work
correctly.
Frequency of those clock can differ from chip to chip, one constant
value from Kconfig may not be best when low power clock (sourced
from RCX or RC32K) is used for system tick.
This code modifies global z_clock_hw_cycles_per_sec variable that
is used when TIMER_READS_ITS_FREQUENCY_AT_RUNTIME is enabled
in Kconfig.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
In preparation for simulated nRF54L targets,
let's add kconfig options aking to the ones
we have for the nRF52 and 53 devices.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add the Kconfig options and use the aliased
addresses for the bootcode regions of the IMX7D
and IMX6SX SOCs to allow the Linux rproc
framework to load the irq-vectors into
the correct memory areas.
Activating this option might enlarge the bin
file if the zephyr,flash and rom_start chosen
region addresses are not matching.
It is up to the user to enable this feature
based on code location choices (OCRAM, DDR, TCM...).
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
Align SYS_CLOCK_HW_CYCLES_PER_SEC with other SMP nSIM
configurations and set it to 1000000.
This significantly reduce verification time on HS5x platforms.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Add DT node entries to RW for DAC and ADC.
Support the SOC required initialization of the DAC and ADC on RW.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Mask for FLEXSPI clock divider was being used when setting the FLEXSPI
clock selector value. Correct this to use the mask for the selector
instead of the divider.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
For DA1469x if PM config is selected PM_DEVICE must also
be selected for GPIO to work when device enters/exists
deep sleep.
Previously GPIO and regulator drivers selected PM_DEVICE
when PM was enabled.
Now it is moved to SOC instead.
PM_DEVICE selection in GPIO could result in circular dependency
for mcux if MEMC_MCUX_FLEXSPI (which is already dependent on PM_DEVICE)
was to be additionally dependent on GPIO.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Currently, only DCD bootheader was supported to configure the SDRAM.
On IMX RT1170, XMCD can be used as an alternative boot header to DCD.
XMCD is more advanced than DCD and enhances SDRAM access speed.
This is benefit for SDRAM access application.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
`SB_CONFIG_VPR_LAUNCHER` can now be used in building a VPR target,
to enable automatic building of image that will launch the VPR.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
iMXRT1042 SOC should be clocked at 528 MHz maximum. Correct the clock
setup to use the system PLL.
Fixes#70755
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow configuration of the system pll on the iMXRT10xx series parts, via
a fractional pll node under the CCM module.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce z_page_frame_set() and z_page_frame_clear() to manipulate
flags. Obtain the virtual address using the existing
z_page_frame_to_virt(). This will make changes to the page frame
structure easier.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The ILM_MAX_SIZE of different chip variants can be declared in the
Kconfig of the respective variant.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Hardware-specific properties should stay in sync with the definitions
provided by MDK. Existing measures for this include:
* The `validate_base_addresses.c` file included in every build;
* The `nordic-nrf-ficr-nrf54h20.h` header generated from SVD.
If there's information that cannot be extracted from SVD, it may have to
be validated against C types. Add `validate_binding_headers.c` for this
purpose, which automagically includes all `dt-bindings` headers included
by DTS in a given build.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
The HAS_MCUX_CSI (as well as all the HAS_MCUX_XXX) config was obsolete
and has been replaced by the DT_HAS_NXP_IMX_CSI_ENABLED (i.e.
DT_HAS_XXX_ENABLED). Drop it as well as all the dependencies on it.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Used multiple places in the tree. The idea is to determine if this node
corresponds to a specific node (e.g: flexspi) so that specific
configurations can get done. Without the fix, the macro expansions were
defaulting to false.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Commit 149df6b61b ("soc: nordic: nrf54h20: Disable USBHS core cache")
inadvertedly removed default MPU regions defined in arm_mpu_regions.c.
Without the SRAM_0 region defined all builds with asserts enabled result
in failed assertion even before the kernel inits. The failed assertion
is the very last step of arch_kernel_init() when MPU areas are marked
for dynamic regions. Because the failure occurs so early, the device
appears completely dead.
Fix the issue by bringing the default regions to nrf54h20 custom
regions file.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Moves a non-SoC Kconfig to the normal Kconfig file, as this symbol
has nothing to do with the SoC selection itself
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add `CHECK_DT_REG()` entries for a few additional peripheral types:
BELLBOARD, CCM, GRTC, HSFLL, UICR, and VPR.
For peripheral instances outside of the Global Domain, such as DPPIC020,
use domain-specific defines like NRF_RADIOCORE_DPPIC020 when validating.
These are always defined by the MDK, while NRF_DPPIC020 isn't guaranteed
to exist in those cases. Revise existing macro checks accordingly.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
If no HSFLL needs trimming, then `trim_hsfll()` should be compiled out.
This makes it easier to reuse the rest of `soc.c` out of tree.
Furthermore, some HSFLL instances can be trimmed before booting Zephyr,
so the FICR client properties in the DT binding should not be required.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
External XTAL usage is missing a Bootstrap Cycle configuration
in Kconfig, causing build to failure when CONFIG_RTC_CLK_SRC_EXT_CRYS
is selected.
Fixes#72190
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Configure USBHS core registers as non-cachable to prevent D-Cache from
inhibiting volatile accesses to the USBHS core registers.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The nRF54H20 implements a variant of the SPI DW peripheral that
has slightly different register layout. Enable it in the defconfig.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Introducing MDIO and PHY support for stm32, phy driver gets
error (-116) if it tries to read phy chip id, since MDIO IP is
part of ETH IP, and eth hw module is still not initialized.
Forcing a priority that allows possibly connected PHY chip to be
detected properly at initial boot.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
The ipc driver device data (struct intel_adsp_ipc_data) contains a
semaphore. Upon device init, the device data is zeroed out. This is safe
for other fields, but the semaphore should be properly initialized
before use.
This lack of initialization leads to a system crash when CONFIG_POLL is
enabled (e.g. to enable CONFIG_SHELL), IPC driver handles an interrupt
and executes k_sem_give() on a uninitialized semaphore object. This will
eventually lead to null dereference in z_handle_obj_poll_events().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
An area of flash memory on the RA4M1 MCU is used to store information
used to configure the device following a reset. This patch instructs
the linker to reserve this memory area and provides kconfig options
that are used to populate it (at build time) with the desired device
configuration.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
This commit updates the device tree and memory header file
for the Intel MTPM 1.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace15_mtpm.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel LNL 2.0 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace20_lnl.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel cAVS 2.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
For CPP application, such as samples/cpp/cpp_synchronization/, it will
report the following building errors:
...
zephyrproject/modules/hal/nxp/imx/devices/MCIMX7D/./MCIMX7D_M4.h:5101:51:
error: 'reinterpret_cast<CCM_Type*>(808976384)' is not a constant
expression
...
The error is caused by commit: 72312feead
" arch: arm: cortex_m: Use cmsis api instead of inline asm in arch_irq_*"
This patch will cause kernel.h includes cmsis_core.h which includes soc.h,
so that soc.h will be used by c++ code.
This patch make soc.h can be c++ compatible.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Adds configuration that allows nRF53 and nRF91-based boards to be
flashed through west using sysbuild for multiple images with the
recover or erase options and prevent running those commands for
each image being flash, which would make the device unbootable.
Also defers reset whilst all images for the cores of these SoCs
are flashed.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The pinctrl driver actually uses SYSCON, so 'depends on' should be used
instead of 'select'. SYSCON should be selected in SoC config instead,
just like other SoC do.
This breaks Kconfig dependency loop for configs that indirectly depends
on SYSCON and causes PINCTRL to be selected.
Signed-off-by: Patryk Duda <patrykd@google.com>
This commit implement the UART asynchronous API mode support.
When the API is used, the UART hardware cooperates with the DMA (MDMA)
module to handle the the data transfer and receiving.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Using the SOC_IT8XXX2_REG_SET_V2 instead of constantly adding new
variants of the IT82XX2 SoC.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This adds automatic GPIO latching before going to extended sleep and
restoring state after wakeup.
Mode and state for each pin is stored, then ports are latched to retain
state when PD_COM is disabled during sleep. On wakeup mode and state for
each pin is restored and ports are unlatched to make it work again.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This enables cache retainability while in sleep so there's no penalty
when executing from QSPI after wakeup.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
This enabled extended sleep for Renesas SmartBond(tm).
Extended sleep is low power mode where ARM core is powered off and can
be woken up by PDC. This is default sleep mode when CONFIG_PM is
enabled.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This adds timer driver for Renesas SmartBond(tm) family.
It uses TIMER2 block which is in PD_TIM power domain so it can work even
if ARM core is disabled, thus can work as a sleep timer.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Remove CONFIG_NRF_ENABLE_ICACHE as it is not needed. There is CONFIG_ICACHE
which is by default enabled for nrf54h.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The AM64x and AM62x are both SOCs from the TI K3 family
and share common architecture designs. The M4F subsystem
is actuall identical on both SOCs.
Therefore, just add all missing CONFIGs, files, etc. to
support the AM6442x SOC.
Since MMR and RAT initialization are identical too, both
functions can be re-used. However, since they might
differ in the future, the am64x has it's own init
function.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
This implements basic driver to utilize the I3C IP block
on NPCX.
1. I3C mode: Main controller mode only.
2. Transfer: Support SDR only.
3. IBI: Support Hot-Join, IBI(MDB).
Controller request is not supported.
4. Support 3 I3C modules:
I3C1(3.3V), I3C2(1.8V, espi mode), (I3C3 1.8V or 3.3V)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
1. The only valid values of MCLKD clock frequency
are between 40Mhz to 50Mhz.
2. If DMA is used, the APB4_CLK clock frequency must
be equal to or higher than 20Mhz.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Prevent the CPU from entering deep doze mode when JTAG debug is enabled.
Additionally, The CPU address from 0x80000800 to 0x800008FF should be
reserved for JTAG debug usage. This commit reserves the area from the end
of the reset section to 0x800008FF if JTAG debug is enabled.
Tested with:
- west build -p always -b it82xx2_evb samples/hello_world/
-DCONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE=y
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Real Time peripherals should be enabled by default.
Add a common initialization point for all VPRs and enable them.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
IRQ handling functions are now in interrupt controller.
Enable necessary KConfigs to support CLIC properly.
A nice side effect of enabling RISCV_PRIVILIGED is that
`vector.S` is no longer necessary as common code handles
that.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Fixed order of mepc and _mcause in esf for 32bit stacking.
Added missing stack pointer alignement bit support.'
Signed-off-by: Lukasz Stepnicki <lukasz.stepnicki@nordicsemi.no>
RISCV_PRIVILEGED implicitly depends on INCLUDE_RESET_VECTOR.
Remove that dependency by adding support for SoCs that
do not need the `__reset` stub.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
For more effective code execution on STM32 devices is convenient
to enable flash prefetch buffer.
To be enabled by default, possible to disable using kconfig.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
