Commit graph

4737 commits

Author SHA1 Message Date
Michael Hope 813465d2fe soc: wch: add support for the HSI, HSE, and LSI clocks
Add support for configuring these clocks at startup, including
selecting which clock feeds the PLL, and which is used as the main
SYSCLK.

Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Michael Hope <mlhx@google.com>
2024-06-24 20:23:39 +02:00
Michael Hope 662569fcc9 boards: add ch32v003evt
Signed-off-by: Michael Hope <mlhx@google.com>
2024-06-24 20:23:38 +02:00
Michael Hope eb5c2250d3 drivers: add ch32v00x pinctrl support
Signed-off-by: Michael Hope <mlhx@google.com>
2024-06-24 20:20:21 +02:00
Michael Hope 57fd9010b8 soc: update the interrupt handling
Signed-off-by: Michael Hope <mlhx@google.com>
2024-06-24 20:20:21 +02:00
Michael Hope 4f05db1cd3 soc: depend on the HAL
Signed-off-by: Michael Hope <mlhx@google.com>
2024-06-24 20:20:20 +02:00
Michael Hope fc1c9ceee8 soc: add wch_ch32v003 stubs
Signed-off-by: Michael Hope <mlhx@google.com>
2024-06-24 20:20:20 +02:00
Martin Tverdal 78d2ed5428 soc/nordic/nr54l: increase flash erase time define
Time it takes to "erase" one "page" of rram is too low.
Where getting timeouts.
"erase" of rram is done by writing all the words.
one "page" is 4096 bytes meaning 1024 32bit words.
worstcase time it takes to write one 32bit word from
0x00000000 to 0xffffffff is about 42us, giving 42ms
to write 1024 words.

Signed-off-by: Martin Tverdal <martin.tverdal@nordicsemi.no>
2024-06-24 08:28:13 -04:00
Romain Pelletant 8e6cff0176 soc: esp32: fix unknown defined for linker
* Fix unknown define at link stage when CONFIG_BT is enabled
Solve #74836

Signed-off-by: Romain Pelletant <romain.pelletant@fullfreqs.com>
2024-06-24 14:25:37 +02:00
Sylvio Alves ee1b13c822 soc: esp32c3: fix tls linking error
Fix linking error due undefined tdata entry.
After #72642, tdata could be undefined due to
missing TLS check.

Fixed #74852

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-06-24 14:25:18 +02:00
Jordan Yates 07870934e3 everywhere: replace double words
Treewide search and replace on a range of double word combinations:
    * `the the`
    * `to to`
    * `if if`
    * `that that`
    * `on on`
    * `is is`
    * `from from`

Signed-off-by: Jordan Yates <jordan@embeint.com>
2024-06-22 05:40:22 -04:00
Andy Ross e9c23274af Revert "soc: intel_adsp: only implement FW_STATUS boot protocol for cavs"
This breaks SOF load on MTL devices.  See SOF bug for details:
https://github.com/thesofproject/sof/issues/9243

This reverts commit fa798ce2d5.

Signed-off-by: Andy Ross <andyross@google.com>
2024-06-21 11:52:38 -04:00
Daniel Leung c44c922198 soc: xtensa/dc233c: remove xtensa_dc233c_stack_ptr_is_sane
The generic stack pointer checker in the architecture code is
enough so we can remove the platform specific one. Besides,
xtensa_dc233c_stack_ptr_is_sane() does not do much checking
either.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-06-21 09:59:36 +02:00
Sylvio Alves b38d4300b9 soc: esp32c3: fix TLS flash addressing
When TLS is used, `__tdata_start` is PROVIDED by
"thread-local-storage.ld" using absolute address, which
makes it land in wrong flash address. This causes risc-v startup
code to fail during memcpy/memset.

This PR overrides `__tdata_start` to use ADDR, which will
make sure it is placed in DROM region due to AT keyword.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-06-20 14:07:54 -04:00
Pieter De Gendt 99366dd2be linker: Add ROM_SECTIONS location
Currently iterable sections as per the documentation are added with
zephyr_linker_sources(SECTIONS ...) after bss/noinit.
This commit allows putting sections after common-rom.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2024-06-20 12:08:58 -04:00
Rafał Kuźnia f7d7cb885f soc: nordic: configure recover run once for nrf54h20
The nrfutil device v2.4.x now supports the recover operation. Configure
run once to ensure that domains are not unnecessarily erased.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2024-06-19 13:24:23 -04:00
Marek Matej e5de9d2447 soc: espressif: esp32: improve memory utilization
Move the user_iram_end boundary to allow more statical allocations.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-19 13:23:47 -04:00
Ioannis Damigos 082e2b706a da1469x: Move enabling PM from board to SoC level
Move enabling PM from board to SoC level

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2024-06-18 14:36:38 -04:00
Ioannis Damigos 0a0bccabd8 drivers/smartbond: Fix PM device runtime support
Removed PM device runtime support from drivers in PD_SYS domain.

Update the rest device drivers to call pm_device_runtime_get/put()
functions when CONFIG_PM_DEVICE_RUNTIME is enabled.

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2024-06-18 14:36:38 -04:00
Yong Cong Sin abbd19c393 drivers: interrupt controller: update GIC Kconfigs
Selection of these GIC Kconfigs have been deprecated
for more than 2 releases, users should use the devicetree
method instead, update the Kconfigs.

The SOCs below have been updated to not select `GIC_V3`, since
their devicetree already have the required compatible:
- fvp_aemv8r
- rzt2m
- rk3658

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-06-18 14:33:58 -04:00
Fin Maaß 3a843f924b dts: riscv: litex: remove atomic extention
remove atomic extention, as the standard
vexriscv has no A.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-18 15:54:46 +02:00
Francois Ramu e58ab6d713 soc: stm32: config DBGMCU register writing for SWO configuration
Some stm32 series, do not have a LL_DBGMCU_SetTracePinAssignment
function  to enable trace IO port, this is the case with the
stm32h7 serie.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-18 15:52:10 +02:00
Flavio Ceolin 490251d779 soc: intel_adsp/ace: Comply with MISRA Rule 14.4
Use boolean type in a controlling expression.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-17 17:46:16 -04:00
Kai Vehmanen 6339609c15 soc: intel_adsp: tools: improve cavstool.py winstream code
Modify the winstream code in cavstool.py to use the Regs helper
class and get rid of byte array access when reading and writing
to winstream headers. This brings the cavstool.py implementation
closer to the Zephyr C reference implementation and ensures
the header fields are read and written to with 32bit access.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-06-15 14:21:02 +02:00
Marek Matej 90ecdf0dab soc: espressif: esp32s2: improve memory layout
- Allow more statical allocations by reordering the sections
  in the mcuboot.ld and in default.ld.
- Reorder the ROM sections to cover the cases described in
  the `common-rom-common-kernel-devices.ld`.
  Changing the order of .rodata and .text we prevents to create an
  overlapped segments issue.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-15 05:19:00 -04:00
Daniel Leung ea3a47e38f soc: intel_adsp/hda: fix range checking
intel_adsp_hda_set_buffer() asserts when the HDA buffer is
outside of RAM space. However, it uses CONFIG_SRAM_SIZE as
if it is bytes. In reality, CONFIG_SRAM_SIZE is in KB so
we need to multiply it by 1024, or simply use marco KB().

Fixes #74250

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-06-15 04:46:04 -04:00
Adam Berlinger 19b39406eb soc: st: Add support for STOP3 on STM32U5
LPTIM is not available in STOP3 mode, so RTC needs to be used instead.
This code usese similar approach as STM32WBAx for suspend to ram.
The STOP3 is disabled by default in device tree.

Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
2024-06-15 04:44:26 -04:00
Swift Tian 81e51f0356 soc: ambiq: Add shared_ram section
Add linker script file shared_ram.ld where defines sections used by
specific peripherals.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>
2024-06-14 21:07:00 -04:00
Sadik Ozer b5fb89cb52 soc: Add the MAX32670 SoC
Add MAX32670 Kconfig and dts files

Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-06-14 21:06:16 -04:00
Evgeniy Paltsev 59667d19ed snps: board: rmx100: add pmp
Add RV PMP to the SoC configuration and to simulator options

Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2024-06-14 21:05:36 -04:00
Nikolay Agishev efedf1cff3 ARCMWDT: Add compiler support for nSIM RMX platform
Add MetaWare compiller support for nSIM RMX platform

Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
2024-06-14 19:01:06 -04:00
Raffael Rostagno 9265c82313 soc: esp32c6: Kconfig and .ld updates, DTS and comments fix
Kconfig, .ld and comments fixing
Fixed address of UART1, WDT and RTC timer disabled by default

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Raffael Rostagno 6096a10b9a drivers: clock_control: Refactor for ESP32C6
Added support for C6 to allow CPU clock config

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Raffael Rostagno 67e43f6a81 drivers: intc: Fix for ESP32C6 interrupt sources allocation
Fix to properly allocate IRQs for interrupt sources over 60.
It also screens out non-allocatable IRQs used by the CPU.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-06-14 18:51:46 -04:00
Marek Matej b3523c9bfa soc: espressif: add esp32-c6 support
Add basic support for esp32c6 SoC.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-14 18:51:46 -04:00
Jiafei Pan 4f034f46b0 soc: imx8mp: enable rdc for enet
Add RDC dts node for ENET and configure it in soc.c.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-06-14 19:21:18 +02:00
Jiafei Pan 3f831e30fa soc: imx8mm/n/p: enable cache driver for Cortex-A Core
Enable Cache driver in hal_nxp.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2024-06-14 19:21:18 +02:00
Grzegorz Swiderski f908b41154 soc: nordic: Resolve z_arm_platform_init in the linker generator
Fixes #72673
Follow-up to #70977 and #71590

The CMake linker generator doesn't have an API equivalent to `PROVIDE`,
but the existing `zephyr_linker_symbol()` function should do just fine.
It still lets us set `z_arm_platform_init = SystemInit` and thus keep
the reduced ROM space.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-06-14 19:16:37 +02:00
Marcel Birthelmer 58a54e3452 soc: samd51: Fix xosc32 initialization
At osc32k_init in the soc_samd5x.c file the start-up value of 7 which
is reserved. This fixes the startup timeout and control gain with the
correct values.

Signed-off-by: Marcel Birthelmer <marcel@carrietech.com>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2024-06-14 15:36:55 +02:00
Anke Xiao 89a0ff8f61 soc: nxp: kinetis: soc.c: configure i2c driver clock
Set the i2c driver clock source when it is Okay.

Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
2024-06-14 11:12:27 +02:00
Daniel Schultz 281500f046 soc: ti: k3: Enable BUILD_NO_GAP_FILL for all M4
By default, a post build step tries to fill gaps in the output
hex file. Since the AM62x, for example, has different,
non-contiguous memory sections, it tries to fill a gap over
multiple GBs. Disable this feature since the K3 architecture has no
dedicated flash for the firmware and stores it in a Linux rootfs.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2024-06-13 20:24:16 -04:00
Sadik Ozer 406764aec6 soc: Add the MAX32672 SoC
Add MAX32672 Kconfig and dts files

Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-06-13 20:17:49 -04:00
Grant Ramsay 5914c86931 arch: treewide: Remove unnessecary flash size/address defconfig when !XIP
FLASH_SIZE=0 and FLASH_BASE_ADDRESS=0 are now the default values
when XIP=n

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2024-06-13 20:15:35 -04:00
Marcin Szymczyk 1d9907a712 soc: common: riscv-privileged: align to no SW ISR table
In case of no SW ISR table, `_isr_wrapper` does not exist.
Do not use it for exception handling.
Future improvements might include setting it to a user-defined handler.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-06-13 16:57:32 -04:00
Marek Matej 51e5f2d3e5 soc: espressif: esp32c3: reorder ROM sections
This covers the cases described in common-rom-common-kernel-devices.ld
Changing the order of .rodata and .text we prevents to create an
overlapped segments issue.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-13 16:47:05 -04:00
Marek Matej 7bf47f8e8f soc: espressif: esp32c3: improve memory utilization
Change the MCUboot segments layout to incread the memory
available in the application.
Add missing symbols to mcuboot.ld

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-13 16:47:05 -04:00
Aksel Skauge Mellbye 2a4417bb8e soc: silabs: Fix CMake test for soc family
Kconfig options need CONFIG_ prefix when tested for in CMakeLists.txt.

Fixes regression introduced in e90c89d453
that causes all apps to fail to initialize on Silabs socs.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2024-06-13 16:42:50 -04:00
Nikodem Kastelik 37e511bcbf soc: nordic: add dmm component
DMM stands for Device Memory Management and its role is to streamline
the process of allocating DMA buffer in correct memory region
and managing the data cache.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2024-06-13 12:02:33 -04:00
Mark Wang 0c70a72ac7 boards: nxp: enable mcux udc on lpc55s69, rt1060 and rt685
set DT node as Okay in board device tree;
add board level's d-cal, txcal45dp and txcal45dm to usbphy node;
enable usb clock; set USB_STACK_USE_DEDICATED_RAM for lpc55s69 and rt685;
load usb.ld for lpc55s69 and rt685.

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2024-06-13 17:59:31 +02:00
Erwan Gouriou 0a8c3a6e27 soc: stm32: Enable prefecth when missing
Enable ART prefetch when not already done.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2024-06-13 08:05:04 -04:00
Erwan Gouriou a4fc1b2cfa soc: stm32c0 Enable ART acceleration
Enable instruction cache as well as prefetch.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2024-06-13 08:05:04 -04:00