Also any demand paging and page frame related bits are
renamed.
This is part of a series to move memory management related
stuff out of the Z_ namespace into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
While all in-tree SoCs have been ported to HWMv2, Zephyr still supports
out-of-tree SoCs in HWMv1 format, including boards. Add a clear
deprecation message so that users get notified that this is a deprecated
feature to be removed in the future.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
During HWMv2 migration, non-ported SoCs were placed in a 'soc_legacy'
folder and sourced from there instead of 'soc' folder.
Remove the no-longer needed soc_legacy folder.
CMake oot SoCs in old hardware model are sourced from
'<soc-root>/soc/<arch>/<soc-path>' which has always been the case, also
before HWMv2.
Remove the 'osource "soc/soc_legacy/...' generation in Kconfig, because
the source is relative to Zephyr base.
All SoCs in Zephyr repository has been ported to the new hardware model
and therefore there is no need for this line.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit enables ISH boards to use APIC timer with TSC time source as
their system timer by replacing CONFIG_HPET with CONFIG_APIC_TIMER_TSC.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
This PR adds support for new Synopsys nSIM RMX100 platform.
New platform based on RISC-V ISA instead of classic ARC.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
Change source tree organization for Synopsys nSIM platform.
Classical ARC architectures arc_v2 arc_v3 moved to arc_classic
SoC and boards family.
nSIM SoCs were separated regarding series: EM, HS, SEM, VPX2.
This PR sould be seeing as the preparation for
addition new nSIM platform based on the RISC-V architecture.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
Replace CONFIG_ESPI_SLAVE by CONFIG_ESPI_TARGET
Replace CONFIG_ESPI_SAF by CONFIG_ESPI_TAF
Replace ESPI_BUS_SAF_NOTIFICATION with ESPI_TAF_BUS_NOTIFICATION in API
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Convert the hci_nxp.c HCI driver to use the new HCI driver API. Also move
the driver binding under dts/bindings/bluetooth, like all other HCI driver
bindings.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
Convert the hci_stm32wba.c driver to the new HCI API. Unlike in most cases,
the devicetree node is already enabled on the SoC level (rather than board
level). This is in order to mirror how the Kconfig option was originally
enabled, i.e. on the SoC level.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
The drivers should be independent after the move to the new HCI driver
API. Having them as a choice also has unexpected consequences with some
drivers being unexpectedly enabled.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
Microchip MEC5 HAL version 0.2 standardizes HAL API and register
define names. Updated the SoC common initialization code using
new HAL API names.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Erase and reset must run only once during flashing.
This prevents a situation, where the next flashed image erases the
previous one.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Until now, the support for Silicon Labs SoCs is limited to the Gecko
families.
This commit allows upstreaming support for non-Gecko based SoCs produced
by Silicon Labs (i.e. SiM3U1xx).
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Add build check that would detect unwanted calls
from the `iram0.loader_text`, which is the last
bootloader segment to be alive.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
When BCM4 bit is set to zero, the hardware semaphore clock is never
enabled on startup. The hardware semaphores might still randomly work,
but very unreliably, and the locking procedure will need several retries
despite no competition on the hardware semaphores. This leads to wasted
clock cycles on the M4 and sometimes even random kernel panics.
This can be solved by always enabling the hardware semaphore clock in
the init procedure of the M4, regardless of whether it is used within
the initialization or not. On the M7, it is already always enabled.
Signed-off-by: Celina Sophie Kalus <hello@celinakalus.de>
The following configuration options:
SYS_CLOCK_HW_CYCLES_PER_SEC
SYS_CLOCK_TICKS_PER_SEC
should get their values according to lp_clock node's
clock-src property.
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
adsp_memory.h is pretty much the same for all ace platforms.
Generalize it getting register address from devicetree and
and move it to a common place.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
A single trigger of the TASK_FREQ_CHANGE task might not be enough, so
trigger twice to make sure the frequency gets updated.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Add devicetree nodes for the Reset Information registers on nRF54H20,
along with a new binding.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Remove dead code that cannot be enabled.
Kconfig prevents us from enabling PM_S2RAM on 53 because it is not
supported any more.
But we still have some dead code left over in soc.c, so we delete this
code.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add the new STM32HRSX serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics
Same MPU regions as stm32h7 device.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
low level 1b: 4mA or 2mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add support for configuration of the ARM PLL on the iMXRT1170/1160
series SOCs. This PLL is used to generate the M7 core frequency, and is
an integer pll. Provide default configurations for the RT1160 and RT1170
targeting 600MHz and 1GHz respectively.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Complete wake-up pins configuration before powering off
the system when the CONFIG_STM32_WKUP_PINS flag is enabled.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Implement GPIO pins configuration as sources for STM32 PWR wake-up pins
behind the scenes exclusively from devicetree information for all series
using the public stm32_pwr_wkup_pin_cfg_gpio() function.
Introduce macros for parsing & storing DT wake-up pins config in C structs.
Introduce user-configurable STM32_WKUP_PINS Kconfig flag.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Before that fix, the SOC was unable to boot properly.
Starting turned directly into z_arm_usage_fault().
Fixes zephyrproject-rtos#73485
Signed-off-by: Sven Ginka <sven.ginka@gmail.com>
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.
As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.
Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases. These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Enable monolithic build for all BLE apps.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Fix linker error caused by the smartbond timer driver
being enabled at the same time as the smartbond timer counter
driver. For some reason putting SMARTBOND_TIMER=n in a conf
file does not fix this, this change has to be made to the
Kconfig.defconfig to not add this default y case in order
to fix the error. At least that is all I could figure out,
and not sure why the .conf doesn't override it.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Created `GEN_OFFSET_STRUCT` & `GEN_NAMED_OFFSET_STRUCT` that
works for `struct`, and remove the use of `z_arch_esf_t`
completely.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The CLIC requires that mtvec.base is aligned to 64 bytes.
_isr_wrapper is used as mtvec.base, so align it to 64 bytes.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
headers for dmic are now part of the SoC and maintained per generation,
so create one header for PTL and build the code for PTL in some of the
drivers (dmic_nhlt).
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds definition of ACE 3.0 Panther Lake board.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
power_down() expects a cached pointer. Fix the sparse annotation
to match the implementation (sys_cache_cached_ptr_get() returns a cached
pointer so this is correct).
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit introduces support for an alternate linking method in the
LLEXT subsystem, called "SLID" (short for Symbol Link Identifier),
enabled by the CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID Kconfig option.
SLID-based linking uses a unique identifier (integer) to identify
exported symbols, instead of using the symbol name as done currently.
This approach provides several benefits:
* linking is faster because the comparison operation to determine
whether we found the correct symbol in the export table is now an
integer compare, instead of a string compare
* binary size is reduced as symbol names can be dropped from the binary
* confidentiality is improved as a side-effect, as symbol names are no
longer present in the binary
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Select the newly introduced nrf54lx compatible kconfig
option.
This is common both for real HW and for simulated HW,
allowing SW to behave appropriately for both.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This is a soc/board integration for the MediaTek Audio DSP device on
the MT8195 SOC, along with a Zephyr mtk_adsp soc integration that will
work to support similar 8186 and 8188 device shortly.
A python loader (similar to cavsload.py) is included that will run in
developer mode on current chromebooks (an HP x360 13b-ca000 was
tested) with an unmodified kernel.
Signed-off-by: Andy Ross <andyross@google.com>
Create a pseudo-terminal to access Zephyr shell on the audio DSP.
The shell terminal is enabled with "-p" command-line option.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Add a new shell backend implemented over a shared memory window
on the Intel audio DSPs. The implementation uses the Zephyr winstream
to manage the data streaming.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
STM32 MCU shall set voltage regulator level with respect to set clock
frequency to reach optimal power consumption.
Voltage regulator is set prior to clock setting based on configuration
from dts/overlay file. Config_regulator_voltage is set as weak in
clock_stm32_ll_common - config_regulator_voltage can be
extended to other STM32 families without need to rewrite heavily
family clock driver, default one can be still used.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Configure CAN120 MCAN core registers as non-cachable to prevent D-Cache
from inhibiting volatile accesses to the CAN120 MCAN registers. Also
apply non-cachable attribute to the message ram region. Even though the
MCAN driver handles cache invalidation/flushing, MPU faults are still
triggered (to be investigated).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Cosmetic change to align code style when initializing DSP registers. The
code in intel_is_ace() branch was moved as-is from acetool.py when the
two tools were merged to make reviewing easier. Fix the code style to be
coherent in the merged cavstool.py. No functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Use the correct register to read ROM status on intel_adsp_ace20.
Without this this fix, firmware load is successful but
boot takes extra 2 seconds and following warning was emitted:
WARNING:cavs-fw:Load failed? ROM_STATUS = 0x0
The log-only mode (-l) was not working at all and is fixed
by this commit.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This adds support for the local APIC in one-shot mode as the timeout
event source for those cases where the CPU supports invariant TSC but
no TSC deadline capability. It is presented as another timer choice.
Existing Kconfig symbols were preserved to minimize board config
disturbance.
This hybrid approach was implemented kind of backward in the apic_timer
driver but it is far cleaner to carry this here.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Added ADI MAX series soc, first partnumber is MAX32690
The family structure will be
ADI_MAX
MAX32xxx
MAX32655
MAX32655EVKIT
MAX32655FTHR
MAX32666
MAX32666FTHR
MAX32666FTHR2
MAX32690
MAX32690EVKIT
MAX78xxx
MAX78000
MAX78002
...
When MAX32 MCUs goes to sleep mode debugger could not access it
and flashing fails, ARM_ON_ENTER_CPU_IDLE_HOOK prevent
the CPU from actually entering sleep
by skipping the WFE/WFI instruction.
Due to ARM_ON_ENTER_CPU_IDLE_HOOK is not configurable at the user
space, added a config wrapper as MAX32_ON_ENTER_CPU_IDLE_HOOK.
If MAX32_ON_ENTER_CPU_IDLE_HOOK config being defined (default y)
devicei will not goes to sleep mode in idle state.
To disable it add below line in your configuration file
CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK=n
MAX32690 has two core Cortex-M4 and Risc-V this commit adds M4 core
support.
Co-authored-by: Jason Murphy <jason.murphy@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The software protocol to write status value of 0x05 (FW_ENTERED)
into memory window 0 at Zephyr boot, is not needed in the ace1.x
boot flow and does not match the semantics host systems are expecting
at this location in the memory window (e.g. write of 0x05 is not
expected).
Make this logic specific to intel_adsp_cavs platforms and move the code
out from common intel_adsp code.
This commit depends on update to cavstool.py to use correct
ROM status register to observe boot state.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Starting with ace1.x, the boot status is no longer reported by
the boot ROM in the SRAM status window as it was done in older
platforms. The current cavstool.py code works on these newer platforms,
as Zephyr soc bootcode writes to same location, but this is not
the recommended boot flow.
Modify boot flow to use a dedicated register to observe boot
state. This change improves usability of cavstool.py on ace1.x
platforms as:
- it is possible to start cavstool.py (e.g. in log-only or shell mode)
while DSP has been already been booted, but is currently in
low-power mode (and SRAM window is not accessible from host)
- more reliable boot and better error reporting as actual ROM
status is observed
Furthermore, this change allows to remove the memory window
writes from Zephyr intel_adsp boot_complete(). This IPC interface
is application and IPC revision specific and the write should not
be done in generic Zephyr SoC code. However, to keep cavstool.py
working, the tool has to be updated first.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit defines the bt-hci subnode under the bleif node on
Ambiq Apollo3 Blue and Apollo3 Blue Plus SOC.
Also add the default configurations for Bluetooth feature on Ambiq
apollo3_evb and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Clock must be restored as soon as the SoC leaves standby.
Keep the logic inside the SoC instead of delegate it to the pm
subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
clocks instead of just one or the other
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.
Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
k_sem_init() is called for every IPC message sent in
intel_adsp_ipc_send_message(). This has not had any side-effects
in upstream configurations, but has been linked to a failing
run of test_obj_tracking_sanity test case in downstream Zephyr
use.
Replace k_sem_init() with k_sem_reset() as this is more appropriate
API to reset the semaphore count, and ensure deterministic
behaviour in case a thread is waiting on the semaphore at time
of reset.
Suggested-by: Peter Mitsis <peter.mitsis@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
