Commit graph

4722 commits

Author SHA1 Message Date
Henrik Brix Andersen 58db527d31 Revert "soc: imx93: enable flexcan driver"
This reverts commit 69360d2f38 which is
causing CI build errors.

Fixes: #73955

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-06-12 11:54:38 +02:00
Jose Alberto Meza f854b8b799 drivers: samples: espi: Adjust terms per eSPI specification 1.5
Replace CONFIG_ESPI_SLAVE by CONFIG_ESPI_TARGET
Replace CONFIG_ESPI_SAF by CONFIG_ESPI_TAF
Replace ESPI_BUS_SAF_NOTIFICATION with ESPI_TAF_BUS_NOTIFICATION in API

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2024-06-11 19:46:08 -04:00
Johan Hedberg fcddefd7f0 Bluetooth: drivers: Convert NXP HCI driver to new API
Convert the hci_nxp.c HCI driver to use the new HCI driver API. Also move
the driver binding under dts/bindings/bluetooth, like all other HCI driver
bindings.

Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
2024-06-11 19:42:49 -04:00
Johan Hedberg b7b606bdaf Bluetooth: drivers: Convert ST STM32WBA driver to new API
Convert the hci_stm32wba.c driver to the new HCI API. Unlike in most cases,
the devicetree node is already enabled on the SoC level (rather than board
level). This is in order to mirror how the Kconfig option was originally
enabled, i.e. on the SoC level.

Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
2024-06-11 19:42:49 -04:00
Johan Hedberg 130ae9e120 Bluetooth: drivers: Convert Ambiq Apollo driver to new API
Convert the Ambiq Apollo HCI driver to the new HCI API.

Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
2024-06-11 19:42:49 -04:00
Johan Hedberg 97c3a1e4be Bluetooth: drivers: hci: Get rid of Kconfig choice
The drivers should be independent after the move to the new HCI driver
API. Having them as a choice also has unexpected consequences with some
drivers being unexpectedly enabled.

Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
2024-06-11 19:42:49 -04:00
Scott Worley 7c0b038d6b soc: microchip: mec: Common SoC init updated to MEC5 HAL v0.2
Microchip MEC5 HAL version 0.2 standardizes HAL API and register
define names. Updated the SoC common initialization code using
new HAL API names.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2024-06-11 20:04:46 +03:00
Emilio Benavente d85cb222e4 drivers: timer: updated lptmr_timer binding
Updated the lptmr timer binding from
nxp,kinetis-lptmr to nxp,lptmr.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2024-06-11 17:04:26 +03:00
Rafał Kuźnia 6551492a3f soc: nordic: configure run once for nrf54h20
Erase and reset must run only once during flashing.
This prevents a situation, where the next flashed image erases the
previous one.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2024-06-11 14:01:35 +01:00
Marcin Szymczyk 41071584a6 soc: nordic: vpr: remove Zifencei RISC-V extension
VPR does not implement Zifencei extension, remove it.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-06-11 03:37:03 -07:00
Reto Schneider e90c89d453 soc: silabs: Remove SOC_VENDOR_SILABS
Until now, the support for Silicon Labs SoCs is limited to the Gecko
families.

This commit allows upstreaming support for non-Gecko based SoCs produced
by Silicon Labs (i.e. SiM3U1xx).

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
2024-06-10 15:15:34 -05:00
Alessandro Manganaro 7e9d07537d soc: st: stm32: stm32wbax: Updating hci interface with Cube FW 1.3.1
Updating hci interface according STM32WBA Cube FW 1.3.1

Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
2024-06-10 15:04:36 -05:00
Marek Matej 9f1a4e3e4f soc: espressif: esp32s3: add cross segment call check
Add build check that would detect unwanted calls
from the `iram0.loader_text`, which is the last
bootloader segment to be alive.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-10 16:58:28 +03:00
Marek Matej 61bb79c7ea soc: espressif: esp32s3: fix memory utilization
Fixed bootloader memory layout.
Improved memory utilization.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-06-10 16:58:28 +03:00
Celina Sophie Kalus a5c67391bb soc: stm32h7: m4: Always enable hardware semaphore clock
When BCM4 bit is set to zero, the hardware semaphore clock is never
enabled on startup. The hardware semaphores might still randomly work,
but very unreliably, and the locking procedure will need several retries
despite no competition on the hardware semaphores. This leads to wasted
clock cycles on the M4 and sometimes even random kernel panics.

This can be solved by always enabling the hardware semaphore clock in
the init procedure of the M4, regardless of whether it is used within
the initialization or not. On the M7, it is already always enabled.

Signed-off-by: Celina Sophie Kalus <hello@celinakalus.de>
2024-06-10 16:56:59 +03:00
nagendra modadugu 161c56fa31 soc: opentitan: update manifest format
Fix calculation of the app entry point.

Signed-off-by: nagendra modadugu <ngm@meta.com>
2024-06-07 19:05:34 -04:00
Anas Nashif 0c0475ff62 soc: xlnx: remove duplicate soc entry
xc7z010 is duplicated.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-06-07 19:02:59 -04:00
Anke Xiao 4873de287a soc: nxp: kinetis: add mke17z9 soc support
Updated the soc.yml and kconfig.soc to support mke17z9

Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
2024-06-07 09:55:56 +02:00
Ioannis Damigos b7fbd91d9e soc/da1469x: Fix CONFIG_SYS_CLOCK_*_PER_SEC defines
The following configuration options:

SYS_CLOCK_HW_CYCLES_PER_SEC
SYS_CLOCK_TICKS_PER_SEC

should get their values according to lp_clock node's
clock-src property.

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2024-06-07 09:54:30 +02:00
Flavio Ceolin 8100871856 soc: intel_adsp: Avoid duplicate adsp_memory_regions
This header is the same for all ACE platforms. Move it
a common folder.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-07 09:52:42 +02:00
Flavio Ceolin 6069f946be soc: intel_adsp: Avoid duplicate header
adsp_memory.h is pretty much the same for all ace platforms.

Generalize it getting register address from devicetree and
and move it to a common place.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-07 09:52:42 +02:00
Stanislav Poboril 5774f47e89 soc: rt11xx: support nxp_enet in soc
Support NXP ENET_1G on RT11xx soc.

Fixes: #66348

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2024-06-06 20:08:27 -04:00
Karsten Koenig 16e7e46478 soc: nordic: nrf54h: Retrigger TASK_FREQ_CHANGE
A single trigger of the TASK_FREQ_CHANGE task might not be enough, so
trigger twice to make sure the frequency gets updated.

Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
2024-06-06 15:21:51 -05:00
Fin Maaß 1d88d7d139 soc: riscv: litex: add reboot
this makes it possible to reboot a
litex SoC.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-06 15:46:40 +01:00
Grzegorz Swiderski 742c728c7e dts: nordic: Add RESETINFO
Add devicetree nodes for the Reset Information registers on nRF54H20,
along with a new binding.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-06-06 10:03:15 +02:00
Sebastian Bøe e1347ded48 soc: nordic: nrf53: Remove broken PM_S2RAM support
Remove dead code that cannot be enabled.

Kconfig prevents us from enabling PM_S2RAM on 53 because it is not
supported any more.

But we still have some dead code left over in soc.c, so we delete this
code.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2024-06-06 10:02:58 +02:00
Francois Ramu f909c4aee2 soc: st: stm32 common soc config introduce stm32h7R/h7S devices
Add the new STM32HRSX serie from STMicroelectronics

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Francois Ramu 4f995bd0ff soc: arm: stm32h7RS introduce stm32h7R/h7S devices
Add the new STM32HRSX serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics
Same MPU regions as stm32h7 device.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Tim Lin 76ced4a82d drivers: pinctrl: ITE: Add a property configure pin current strength
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
           low  level 1b: 4mA or 2mA

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-06-06 00:41:35 -07:00
Daniel DeGrasse c77b956de5 soc: nxp: imxrt11xx: support configuration of ARM PLL
Add support for configuration of the ARM PLL on the iMXRT1170/1160
series SOCs. This PLL is used to generate the M7 core frequency, and is
an integer pll. Provide default configurations for the RT1160 and RT1170
targeting 600MHz and 1GHz respectively.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-06-06 00:41:17 -07:00
IBEN EL HADJ MESSAOUD Marwa 1e556a85df soc: st: stm32: add stm32h533xx support
Add STM32H533XX familly support

Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
2024-06-05 17:36:43 -05:00
Abderrahmane Jarmouni 323fcf94f9 soc: st: stm32: complete wkup pins cfg before poweroff
Complete wake-up pins configuration before powering off
the system when the CONFIG_STM32_WKUP_PINS flag is enabled.

Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
2024-06-05 17:35:55 -05:00
Abderrahmane Jarmouni ae17e48036 soc: st: stm32: common: introduce a wake-up pins driver
Implement GPIO pins configuration as sources for STM32 PWR wake-up pins
behind the scenes exclusively from devicetree information for all series
using the public stm32_pwr_wkup_pin_cfg_gpio() function.
Introduce macros for parsing & storing DT wake-up pins config in C structs.
Introduce user-configurable STM32_WKUP_PINS Kconfig flag.

Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
2024-06-05 17:35:55 -05:00
Sven Ginka c3d7b1c978 soc: atmel: sam: Add invalidate d-cache at z_arm_platform_init
Before that fix, the SOC was unable to boot properly.
Starting turned directly into z_arm_usage_fault().
Fixes zephyrproject-rtos#73485

Signed-off-by: Sven Ginka <sven.ginka@gmail.com>
2024-06-04 22:41:06 -04:00
Peter Mitsis 0bcdae2c62 kernel: Add CONFIG_ARCH_HAS_DIRECTED_IPIS
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.

As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.

Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases.  These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2024-06-04 22:35:54 -04:00
Chekhov Ma 69360d2f38 soc: imx93: enable flexcan driver
- Add flexcan dts node and pinctrl.

Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
2024-06-04 19:14:16 -04:00
Axel Le Bourhis ca53f5ee8e soc: rw6xx: Enable NXP_BLE_MONOLITHIC
Enable monolithic build for all BLE apps.

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
2024-06-04 19:12:45 -04:00
Sadik Ozer 6a8674ce12 soc: Add the MAX32680 SoC
Add MAX32680 Kconfig and dts files

Co-authored-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-06-04 19:12:21 -04:00
Declan Snyder e8a71d9d83 soc: renesas: Fix linker error from multiple IRQ17
Fix linker error caused by the smartbond timer driver
being enabled at the same time as the smartbond timer counter
driver. For some reason putting SMARTBOND_TIMER=n in a conf
file does not fix this, this change has to be made to the
Kconfig.defconfig to not add this default y case in order
to fix the error. At least that is all I could figure out,
and not sure why the .conf doesn't override it.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-06-04 14:04:09 -05:00
Kai Vehmanen 6ad9b6ccab soc: intel_adsp: tools: add intel_adsp_ace30 support to cavstool.py
Add support for intel_adsp_ace30 platforms into cavstool.py.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-06-04 14:03:32 -05:00
Yong Cong Sin 6a3cb93d88 arch: remove the use of z_arch_esf_t completely from internal
Created `GEN_OFFSET_STRUCT` & `GEN_NAMED_OFFSET_STRUCT` that
works for `struct`, and remove the use of `z_arch_esf_t`
completely.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-06-04 14:02:51 -05:00
Yong Cong Sin 3998e18ec4 arch: rename all esf struct to struct arch_esf
Rename every architecture's esf struct to `struct esf`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-06-04 14:02:51 -05:00
Ian Morris 422a709d92 soc: renesas: ra: added support for segger rtt
Added support for Segger RTT to Renesas RA family of Microcontrollers.

Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
2024-06-04 14:00:30 -05:00
Nazar Palamar 7c3b66eac8 soc: psoc6: update pinctrl for PSoC6 MCU (legacy)
update pinctrl for PSoC6 MCU (legacy)

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2024-06-04 16:35:39 +02:00
Piotr Wojnarowski 0f3fe4daab riscv: Align _isr_wrapper to 64 bytes for CLIC
The CLIC requires that mtvec.base is aligned to 64 bytes.
_isr_wrapper is used as mtvec.base, so align it to 64 bytes.

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2024-06-04 13:41:49 +02:00
Sadik Ozer 84a0dee00b soc: Add the MAX32655 SoC
Add MAX32655 Kconfig and dts files

Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Co-authored-by: Okan Sahin <okan.sahin@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-06-04 13:40:44 +02:00
Flavio Ceolin adabe57f4d soc: intel_adsp/ace: Fix SOC_TOOLCHAIN_NAME symbol
Set the appropriated toolchain name for each ace target.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-04 13:40:04 +02:00
Anas Nashif d35a2b89f3 intel_adsp: dmic: enable support for ptl use new headers
headers for dmic are now part of the SoC and maintained per generation,
so create one header for PTL and build the code for PTL in some of the
drivers (dmic_nhlt).

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-06-04 13:40:04 +02:00
Flavio Ceolin 9637b8b0bc intel_adsp: ace30: Bring up ACE 3.0 (PTL)
This commit adds definition of ACE 3.0 Panther Lake board.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-06-04 13:40:04 +02:00
Kai Vehmanen 1541fe9e2f intel_adsp/ace: power: fix address space annotation for powerdown
power_down() expects a cached pointer. Fix the sparse annotation
to match the implementation (sys_cache_cached_ptr_get() returns a cached
pointer so this is correct).

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-06-03 16:07:28 -04:00
Mathieu Choplain 8aa6ae43ce llext: add support for SLID-based linking
This commit introduces support for an alternate linking method in the
LLEXT subsystem, called "SLID" (short for Symbol Link Identifier),
enabled by the CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID Kconfig option.

SLID-based linking uses a unique identifier (integer) to identify
exported symbols, instead of using the symbol name as done currently.
This approach provides several benefits:
 * linking is faster because the comparison operation to determine
   whether we found the correct symbol in the export table is now an
   integer compare, instead of a string compare
 * binary size is reduced as symbol names can be dropped from the binary
 * confidentiality is improved as a side-effect, as symbol names are no
   longer present in the binary

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2024-06-03 15:29:34 -04:00
Vinayak Kariappa Chettimada fb774fef74 soc: nordic: Select new nrf54lx compatible kconfig option
Select the newly introduced nrf54lx compatible kconfig
option.

This is common both for real HW and for simulated HW,
allowing SW to behave appropriately for both.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2024-06-03 03:01:36 -07:00
Andy Ross df8395e3d8 soc: boards: Add MediaTek MT8195 Audio DSP
This is a soc/board integration for the MediaTek Audio DSP device on
the MT8195 SOC, along with a Zephyr mtk_adsp soc integration that will
work to support similar 8186 and 8188 device shortly.

A python loader (similar to cavsload.py) is included that will run in
developer mode on current chromebooks (an HP x360 13b-ca000 was
tested) with an unmodified kernel.

Signed-off-by: Andy Ross <andyross@google.com>
2024-06-01 05:40:05 -07:00
Anke Xiao b84b6de76c soc: nxp: kinetis: add soc support for mke17z7
Added soc support for mke17z7

Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
2024-05-31 16:31:33 -05:00
Kai Vehmanen 5a7600bec6 soc: intel_adsp: tools: add shell support to cavstool.py
Create a pseudo-terminal to access Zephyr shell on the audio DSP.
The shell terminal is enabled with "-p" command-line option.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-31 08:07:03 +02:00
Kai Vehmanen 6509b8199b shell: add shell backend for audio DSP using shared memory window
Add a new shell backend implemented over a shared memory window
on the Intel audio DSPs. The implementation uses the Zephyr winstream
to manage the data streaming.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-31 08:07:03 +02:00
Lubos Koudelka 88de80b774 drivers: clock_control: stm32: adding config_regulator_voltage for L0
STM32 MCU shall set voltage regulator level with respect to set clock
frequency to reach optimal power consumption.
Voltage regulator is set prior to clock setting based on configuration
from dts/overlay file. Config_regulator_voltage is set as weak in
clock_stm32_ll_common - config_regulator_voltage can be
extended to other STM32 families without need to rewrite heavily
family clock driver, default one can be still used.

Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
2024-05-30 09:47:12 -05:00
Gerard Marull-Paretas 3731a137e7 soc: nordic: nrf54h: disable CAN120 MCAN cache
Configure CAN120 MCAN core registers as non-cachable to prevent D-Cache
from inhibiting volatile accesses to the CAN120 MCAN registers. Also
apply non-cachable attribute to the message ram region. Even though the
MCAN driver handles cache invalidation/flushing, MPU faults are still
triggered (to be investigated).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-05-30 05:20:50 -07:00
Romain Pelletant 202c16008f soc: stm32c0: add poweroff mode
Add poweroff mode support for STM32C0
Fixes #73371

Signed-off-by: Romain Pelletant <romainp@kickmaker.net>
2024-05-30 08:59:50 +02:00
Kai Vehmanen db00b813f0 soc: intel_adsp: tools: align code style in maps_regs()
Cosmetic change to align code style when initializing DSP registers. The
code in intel_is_ace() branch was moved as-is from acetool.py when the
two tools were merged to make reviewing easier. Fix the code style to be
coherent in the merged cavstool.py. No functional change.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-29 10:47:29 -07:00
Kai Vehmanen 44dd5a4da9 soc: intel_adsp: tools: fix ace20 fw load flow
Use the correct register to read ROM status on intel_adsp_ace20.

Without this this fix, firmware load is successful but
boot takes extra 2 seconds and following warning was emitted:

WARNING:cavs-fw:Load failed?  ROM_STATUS = 0x0

The log-only mode (-l) was not working at all and is fixed
by this commit.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-29 10:47:29 -07:00
Nicolas Pitre 3c2e57c923 drivers/timer/apic_tsc: use ICR as a fallback timeout event source
This adds support for the local APIC in one-shot mode as the timeout
event source for those cases where the CPU supports invariant TSC but
no TSC deadline capability. It is presented as another timer choice.
Existing Kconfig symbols were preserved to minimize board config
disturbance.

This hybrid approach was implemented kind of backward in the apic_timer
driver but it is far cleaner to carry this here.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-05-29 08:40:43 +02:00
Sadik Ozer d33d5b3a79 soc: Add the MAX32690 SoC
Added ADI MAX series soc, first partnumber is MAX32690
The family structure will be
ADI_MAX
  MAX32xxx
    MAX32655
      MAX32655EVKIT
      MAX32655FTHR
    MAX32666
      MAX32666FTHR
      MAX32666FTHR2
    MAX32690
      MAX32690EVKIT
  MAX78xxx
    MAX78000
    MAX78002
        ...

When MAX32 MCUs goes to sleep mode debugger could not access it
and flashing fails, ARM_ON_ENTER_CPU_IDLE_HOOK prevent
the CPU from actually entering sleep
by skipping the WFE/WFI instruction.
Due to ARM_ON_ENTER_CPU_IDLE_HOOK is not configurable at the user
space, added a config wrapper as MAX32_ON_ENTER_CPU_IDLE_HOOK.

If MAX32_ON_ENTER_CPU_IDLE_HOOK config being defined (default y)
devicei will not goes to sleep mode in idle state.

To disable it add below line in your configuration file
CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK=n

MAX32690 has two core Cortex-M4 and Risc-V this commit adds M4 core
support.

Co-authored-by: Jason Murphy <jason.murphy@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-05-29 07:30:12 +02:00
Sadik Ozer f76256d2f1 drivers: Add MAX32690 pinctrl driver
Pincontrol driver for MAX32690

Co-authored-by: Okan Sahin <okan.sahin@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
2024-05-29 07:30:12 +02:00
Yong Cong Sin 0dac6c132b build: namespace autoconf.h with zephyr/
Namespace the generated `autoconf.h` file with `zephyr/`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-28 22:03:55 +02:00
Yong Cong Sin bbe5e1e6eb build: namespace the generated headers with zephyr/
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.

Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.

Updated the includes path of in-tree sources accordingly.

Most of the changes here are scripted, check the PR for more
info.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-28 22:03:55 +02:00
Alvis Sun 03580e4a1b drivers: i3c: npcx: add HDR-DDR mode for transfer
1. Support HDR-DDR DMA transfer.
2. Remove polling mode in transfer.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
2024-05-28 09:54:03 +02:00
Kai Vehmanen fa798ce2d5 soc: intel_adsp: only implement FW_STATUS boot protocol for cavs
The software protocol to write status value of 0x05 (FW_ENTERED)
into memory window 0 at Zephyr boot, is not needed in the ace1.x
boot flow and does not match the semantics host systems are expecting
at this location in the memory window (e.g. write of 0x05 is not
expected).

Make this logic specific to intel_adsp_cavs platforms and move the code
out from common intel_adsp code.

This commit depends on update to cavstool.py to use correct
ROM status register to observe boot state.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-27 08:16:10 -07:00
Kai Vehmanen 8fc76f1b6d soc: intel_adsp: tools: improve FW boot handling on ace1.x
Starting with ace1.x, the boot status is no longer reported by
the boot ROM in the SRAM status window as it was done in older
platforms. The current cavstool.py code works on these newer platforms,
as Zephyr soc bootcode writes to same location, but this is not
the recommended boot flow.

Modify boot flow to use a dedicated register to observe boot
state. This change improves usability of cavstool.py on ace1.x
platforms as:
 - it is possible to start cavstool.py (e.g. in log-only or shell mode)
   while DSP has been already been booted, but is currently in
   low-power mode (and SRAM window is not accessible from host)
 - more reliable boot and better error reporting as actual ROM
   status is observed

Furthermore, this change allows to remove the memory window
writes from Zephyr intel_adsp boot_complete(). This IPC interface
is application and IPC revision specific and the write should not
be done in generic Zephyr SoC code. However, to keep cavstool.py
working, the tool has to be updated first.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-27 08:16:10 -07:00
Erwan Gouriou 101f791994 soc: stm32: common: Fix proprocessor if/else flow
No reason to be more complex than it should be.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2024-05-27 08:15:59 -07:00
Erwan Gouriou 0620cd9912 soc: stm32: common: Fix Kconfig symbol usage
These symbols don't exist.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2024-05-27 08:15:59 -07:00
Aaron Ye 69d790b293 dts: arm: ambiq: add bt-hci subnode for Apollo3 Blue SOC
This commit defines the bt-hci subnode under the bleif node on
Ambiq Apollo3 Blue and Apollo3 Blue Plus SOC.
Also add the default configurations for Bluetooth feature on Ambiq
apollo3_evb and apollo3p_evb.

Signed-off-by: Aaron Ye <aye@ambiq.com>
2024-05-27 03:27:43 -07:00
Flavio Ceolin e1685bb421 stm32: power: SoC restores the clock
Clock must be restored as soon as the SoC leaves standby.
Keep the logic inside the SoC instead of delegate it to the pm
subsystem.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-27 02:10:03 -07:00
Flavio Ceolin 5ca3bc92c8 intel_adsp: power: SoC restores the clock
The SoC restores the clock only when leaving soft-off only.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-27 02:10:03 -07:00
Lucas Tamborrino e282b0ea84 soc: esp32xx: refactor clock and RTC subsystems
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.

This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.

It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-05-27 01:37:18 -07:00
Yassine El Aissaoui 63791f2817 soc: rw61x: Add BLE support for rw61x
- Add SMU regions
- Add HCI definition
- Add config when BT is enabled

Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
2024-05-25 11:23:04 +03:00
Sreeram Tatapudi f96e6ccbc0 boards: arm: Introduce Infineon CYW920829M2EVK-02 board
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
  clocks instead of just one or the other

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2024-05-24 18:05:11 -04:00
Andrzej Kaczmarek a6e17b34f6 soc: renesas: smartbond: Fix exiting from suspend state
We need to enable irqs that were disabled when entering suspend state.

Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
2024-05-24 18:00:23 -04:00
Flavio Ceolin f54232e912 intel_adsp/ace: power: Do not re-implement cache func
Do not re-implement a function to get a cached pointer. Zephyr cache
API already provides it.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Flavio Ceolin b496d0e52d intel_adsp/ace: pm: Remove unnecessary cache flush
soc_cpus_active is not in cached memory.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Flavio Ceolin c335cb542c intel_adsp/ace: pm: Keep irq locked until restore context
Keep interruptions locked until we properly restore the core
context.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Flavio Ceolin e728adffd2 intel_adsp/ace: pm: Remove unnecessary cache flush
core_desc is not located (nor is accessed) in cached memory.
There is no need to flush it.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Flavio Ceolin 301055dec0 intel-adsp/ace: pm: Only core 0 can d0i3
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.

Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
Piotr Kosycarz 146195a647 soc: nordic: configure run once for nrf54l15
Needed to support sysbuild (app + flpr) with --erase option.

Signed-off-by: Piotr Kosycarz <piotr.kosycarz@nordicsemi.no>
2024-05-23 11:51:31 -04:00
Kai Vehmanen 991b3623b0 soc: intel_adsp: ipc: don't call k_sem_init() multiple times
k_sem_init() is called for every IPC message sent in
intel_adsp_ipc_send_message(). This has not had any side-effects
in upstream configurations, but has been linked to a failing
run of test_obj_tracking_sanity test case in downstream Zephyr
use.

Replace k_sem_init() with k_sem_reset() as this is more appropriate
API to reset the semaphore count, and ensure deterministic
behaviour in case a thread is waiting on the semaphore at time
of reset.

Suggested-by: Peter Mitsis <peter.mitsis@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-23 11:50:50 -04:00
Aurelien Jarno fac04490a4 soc: st: stm32: stm32g0x: enable ART flash cache accelerator
Enable instruction cache and prefetching on STM32G0X SoC family.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2024-05-23 07:50:20 -04:00
Emilio Benavente 552008cf42 soc: nxp: kinetis: added soc support for ke1xz platforms.
Adding supporting soc files for the ke1xz platforms
updating soc.yaml and kinetis soc files
to support ke1xz.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Pavel Krenek <pavel.krenek@nxp.com>
2024-05-22 15:42:48 -04:00
Andy Ross 7dd4c4d312 soc/qemu_xtensa_dc233c: Use the automatically-generated vector region
Remove all the hard-configured absolute addresses and zillions of tiny
ELF segments in favor of the auto-generated vector region, which is
guaranteed correct as long as core-isa.h is matched to the target.

Signed-off-by: Andy Ross <andyross@google.com>
2024-05-22 13:39:47 -05:00
Phi Bang Nguyen 61a16be840 soc: nxp: imxrt11xx: Enable power, clocks and muxing for MIPI CSI-2 Rx
Enable power and clocks for MIPI CSI-2 Rx.
Configure Video Mux to connect it to CSI.

Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
2024-05-21 15:19:52 -07:00
Declan Snyder 5edaa5e276 soc: lpc: Remove peripheral reset code from soc.c
Remove peripheral reset code from soc.c, it should
be handled by driver inits.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-05-21 16:49:42 -04:00
Declan Snyder 488760638d soc: nxp: rw: Add flash config header
Add header file for flash configuration blocks
which is an image header consumed by the RW bootrom.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-05-21 16:48:14 -04:00
Scott Worley c6e3bc3252 soc: microchip: mec: Add new HAL based MEC5 family chips
Add new Microchip MEC chips using the new MEC5 HAL and
add a HAL version of a legacy chip named MECH172x.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2024-05-21 16:45:30 -04:00
Adrian Warecki 369a3a1675 soc: intel: adsp: tgl: ace: Set correct virtual memory size
Corrected virtual memory size to match the range supported by the
Translation Lookup Buffer. The TLB size is 16 MB, however the first 128 KB
is dedicated to LPSRAM and bypasses the TLB. This was taken into account in
KERNEL_VM_BASE, so KERNEL_VM_SIZE was reduced accordingly.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2024-05-21 18:43:37 +02:00
Ioannis Damigos 8716b6a900 soc/da1469x: Take PD_SYS control only once during initialization
Take PD_SYS control only once during initialization

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2024-05-21 11:30:14 +01:00
Nazar Palamar 879c10d818 soc: infineon: port Infineon SOC to HWMv2
Port Infineon SOC to HWMv2.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2024-05-21 11:29:49 +01:00
Tom Chang fe138fc246 drivers: espi: npcx: update espi taf driver
This CL updates the read, write, erase, and get_channel_status
implementations of NPCX chip.

Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
2024-05-20 20:52:35 -04:00
Andy Ross 1472195197 soc/qemu_xtensa_dc233c: Use auto-generated interrupt handlers
The script runs as part of the build now.  Use that feature and
remove the old static file from the manually-run script.

Signed-off-by: Andy Ross <andyross@google.com>
2024-05-20 20:50:55 -04:00
Kai Vehmanen 0ca7ef78bc soc: intel_adsp: tools: merge cavstool.py and acetool.py code
Merge codebases of cavstool.py and acetool.py as the two have
a lot of duplicated code.

To ease with transition, keep acetool.py around with implementation
imported from cavstool.py. This will help to keep any automated
testing flows working that assume both tools exist.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-19 10:56:37 +03:00
Yong Cong Sin cc1894b844 soc: nxp: rw: remove DT_NODE_HAS_STATUS_OKAY
We do not have `DT_NODE_HAS_STATUS_OKAY`, change that to
`DT_NODE_HAS_STATUS(node_id, okay)` instead

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-18 15:51:09 +03:00
Rafał Kuźnia 9cba85bb8d soc: nrf54h: use word accesses to SPI_DW peripheral
The nRF54H20 EXMIF peripheral requires word accesses. Doing accesses of
byte or half-word sizes results in bus fault.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2024-05-17 16:18:56 +01:00