Adds configuration that allows nRF53 and nRF91-based boards to be
flashed through west using sysbuild for multiple images with the
recover or erase options and prevent running those commands for
each image being flash, which would make the device unbootable.
Also defers reset whilst all images for the cores of these SoCs
are flashed.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The pinctrl driver actually uses SYSCON, so 'depends on' should be used
instead of 'select'. SYSCON should be selected in SoC config instead,
just like other SoC do.
This breaks Kconfig dependency loop for configs that indirectly depends
on SYSCON and causes PINCTRL to be selected.
Signed-off-by: Patryk Duda <patrykd@google.com>
This commit implement the UART asynchronous API mode support.
When the API is used, the UART hardware cooperates with the DMA (MDMA)
module to handle the the data transfer and receiving.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Using the SOC_IT8XXX2_REG_SET_V2 instead of constantly adding new
variants of the IT82XX2 SoC.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This adds automatic GPIO latching before going to extended sleep and
restoring state after wakeup.
Mode and state for each pin is stored, then ports are latched to retain
state when PD_COM is disabled during sleep. On wakeup mode and state for
each pin is restored and ports are unlatched to make it work again.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This enables cache retainability while in sleep so there's no penalty
when executing from QSPI after wakeup.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
This enabled extended sleep for Renesas SmartBond(tm).
Extended sleep is low power mode where ARM core is powered off and can
be woken up by PDC. This is default sleep mode when CONFIG_PM is
enabled.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This adds timer driver for Renesas SmartBond(tm) family.
It uses TIMER2 block which is in PD_TIM power domain so it can work even
if ARM core is disabled, thus can work as a sleep timer.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Remove CONFIG_NRF_ENABLE_ICACHE as it is not needed. There is CONFIG_ICACHE
which is by default enabled for nrf54h.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The AM64x and AM62x are both SOCs from the TI K3 family
and share common architecture designs. The M4F subsystem
is actuall identical on both SOCs.
Therefore, just add all missing CONFIGs, files, etc. to
support the AM6442x SOC.
Since MMR and RAT initialization are identical too, both
functions can be re-used. However, since they might
differ in the future, the am64x has it's own init
function.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
This implements basic driver to utilize the I3C IP block
on NPCX.
1. I3C mode: Main controller mode only.
2. Transfer: Support SDR only.
3. IBI: Support Hot-Join, IBI(MDB).
Controller request is not supported.
4. Support 3 I3C modules:
I3C1(3.3V), I3C2(1.8V, espi mode), (I3C3 1.8V or 3.3V)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
1. The only valid values of MCLKD clock frequency
are between 40Mhz to 50Mhz.
2. If DMA is used, the APB4_CLK clock frequency must
be equal to or higher than 20Mhz.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Prevent the CPU from entering deep doze mode when JTAG debug is enabled.
Additionally, The CPU address from 0x80000800 to 0x800008FF should be
reserved for JTAG debug usage. This commit reserves the area from the end
of the reset section to 0x800008FF if JTAG debug is enabled.
Tested with:
- west build -p always -b it82xx2_evb samples/hello_world/
-DCONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE=y
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Real Time peripherals should be enabled by default.
Add a common initialization point for all VPRs and enable them.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
IRQ handling functions are now in interrupt controller.
Enable necessary KConfigs to support CLIC properly.
A nice side effect of enabling RISCV_PRIVILIGED is that
`vector.S` is no longer necessary as common code handles
that.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Fixed order of mepc and _mcause in esf for 32bit stacking.
Added missing stack pointer alignement bit support.'
Signed-off-by: Lukasz Stepnicki <lukasz.stepnicki@nordicsemi.no>
RISCV_PRIVILEGED implicitly depends on INCLUDE_RESET_VECTOR.
Remove that dependency by adding support for SoCs that
do not need the `__reset` stub.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
For more effective code execution on STM32 devices is convenient
to enable flash prefetch buffer.
To be enabled by default, possible to disable using kconfig.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Fixes#71511
Follow-up to #70977
Update the approach by moving the `PROVIDE` directive to a separate
linker script added using `zephyr_linker_sources()`. This makes the
change more likely to propagate to existing samples which are using
CONFIG_CUSTOM_LINKER_SCRIPT.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Move the cache size set calls from soc.c do common loader.c
for all related SOCs. Remove unnecessary includes.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The dependencies should be in a 'depends on' clause.
Also, 'depends on PTP_CLOCK' is redundant because this is
within 'if PTP_CLOCK' already.
Additionally, conditionally include the PTP header in the mac driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Variant chip has different USBPD HW PHY, so FW needs
to apply different downstream CONFIG settings based on
the PHY version.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Nuvoton NPCX chips have reset registers which allow to reset the
peripheral hardware modules. This commit adds the support by
implementing the reset driver. Note that only the reset_line_toggle API
is supported because of the nature of the reset controller's design.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This change reduces the need for core specific conditional compilation and
unifies irq locking code.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
# Conflicts:
# soc/arm/nordic_nrf/nrf53/soc_cpu_idle.h
A workaround to avoid icache corruption was added in commit be881d4cf2
("arch: xtensa: add isync to interrupt vector").
This patch implements a different workaround by adding custom logic to
idle entry on affected Intel ADSP platforms. To safely enter "waiti"
when clock gating is enabled, we need to ensure icache is both unlocked
and invalidated upon entry.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit introduces a common API for managing nRF53 SoC network CPU
Force-OFF state.
From the application CPU point of view, the network CPU is a shared
resource used by multiple users. The current solution where every user
controls the network core state directly leads to dependencies between
users and does not scale well.
To address this problem there should be a single entity responsible for
controlling the network CPU Force-OFF signal. This commit introduces
such module.
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Add code to clock and release reset signal for USBOTG controller on
RW6xx SOC when USB is enabled, and add KConfig selection to indicate to
build system which USB controller this SOC uses.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
IPC has inverted the usage of the state lock API.
In this API semantics, the get method disallow the policy of
using the given state, while the put() release this constraint.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Fix the inline documentation to match implementation. As IPFL is used,
the correct matching function is xthal_icache_region_lock().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Fix the inline documentation to match implementation. As IPFL is used,
the correct matching function is xthal_icache_region_lock().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Nordic SoCs use this hook to execute `SystemInit` as early as possible
after ARM core reset. Previously, `z_arm_platform_init` was defined as
assembly code, which would simply jump to the other function.
However, this extra code can be avoided by using `SystemInit` directly
in place of the `z_arm_platform_init` symbol (whenever it's undefined).
This is now done with a linker script containing a `PROVIDE` directive.
This saves 4 bytes of ROM (0-16 depending on alignment) and also makes
it possible to override `z_arm_platform_init` out of tree, if needed.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
We need to use correct SOC name when naming the Kconfig.defconfig*
files.
So we need the following changes:
- mimx8mp -> mimx8ml8
- mimx8mm -> imx8mm6
- mimx8mn -> mimx8mn6
- mimx8mq -> mimx8mq6
Then we also need to take care of qualifiers name. Standard notation
uses "_" instead of "."
e.g : Kconfig.defconfig.mimx8mp.a53 -> Kconfig.defconfig.mimx8ml8_a53
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Checking if the device state is locked is not correct, device runtime
put / get is no longer checking for it and the only place that was
locking device's state was the pm action callback and if the idea
was to protect some concurrent call, using it is not enough.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
There is no needed to lock/unlock a device state in its pm action
callback. The power management subsystem should take care of
serialize these calls.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Prevent the system from entering runtime idle state during IPC
transactions until the HOST acknowledgment is received.
This patch modifies the IPC mechanism to:
- Lock the runtime idle state immediately after sending an IPC message
to the HOST, preventing the system from entering a low-power state.
- Unlock the runtime idle state once the IPC transaction is acknowledged
by the HOST, allowing the system to enter low-power states if
conditions permit.
The changes ensure that the DSP does not enter a power state that could
interrupt the IPC communication process, maintaining the integrity of
the IPC state machine.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to load without 2nd stage
bootloader.
Update common architecture loader to support all build scenarios.
- simple boot: using single binary application without bootloader
- mcuboot: zephyr port of MCUboot
- application: loaded by the MCUboot
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit removes the `Kconfig.core` file. It's been largely unused, and
the only symbol it provides (`RISCV_CORE_E31`) overlaps with the SoC-layer
provided `SOC_SERIES_SIFIVE_FREEDOM_FE300`.
As of date, the only SoC that uses the E31 core in Zephyr is the FE310 SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
DMASEC is set to non-secure by default, which prevents CCM from
accessing secure memory. Change DMASEC to secure.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The soc_secure_* function are used by the non-secure application
to access hardware resources which are mapped as secure.
Using these functions for hardware resources mapped as non-secure
is missleading.
We have some soc_secure_* functions which read FICR values.
In nRF91 and nRF53 platforms this made sense since FICR
has hardware fixed mapping as secure.
For nRF54 though the FICR has hardware fixed mapping as non-secure.
This change refactors the soc_secure.h to exclude the functions
which read FICR values from being included when FICR is mapped as
non-secure.
Also updates the hwinfo and ieee802154 drivers to adjust to this change.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
In preparation for adding AMP support for i.MX RT6xx family we need
to rename existing cm33 support files to more specific names.
e.g mimxrt685_evk.dts -> mimxrt685_evk_mimxrt685s_cm33.dts
This will allow us to later add support for Cadence DSP found on i.MX
RT6xx series.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
imxrt6xx are dual core devices featuring an ARM Cortex-M33
core and an Cadence Xtensa HIFI4 Audio DSP.
Currently only m33 core is supported. In order to support
the Cadence DSP we need first to do some code-reorganization
for m33.
We start by moving all cm33 related code to its own directory
and introduce the cpuclusters property in soc.yml file.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Clarify usage of __rom_region_end/size in XIP system.
When PMP is enabled, __rom_region_end should be padded to meet the
requirement of PMP entry, and the actual ROM region usage ends at
.last_section instead of __rom_region_end.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Updated ROM region padding to utilize LMA instead of location counter,
because the location counter has been assigned to 'RAM_BASE'.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
LPFlexcomm is a MFD device hence select this Kconfig whenever
it is enabled.
Remove the selection from the individual driver Kconfig files.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Change, for audio DSP and M7 cores, SOC_<name> to match
the exact soc name.
Update the board files accordingly.
These configs are used in SOF and NXP_HAL, so change
sha for these modules.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Enable sleep mode on LPC55S69 (corresponding to zephyr's runtime idle
mode). Add DT description and power api implementations.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Timing function need Cycle Count Register CYCCNT of DWT,
but Arm-Cortex-M23 only support DWT_CTRL, DWT_PCSR and DWT_COMP
& DWT_FUNCTION registers. It can't meet the requirement of timing
function, so to remove CPU_CORTEX_M_HAS_DWT.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
During the migration to Hw model V2 the PR #63495
was not fully reported.
This change is adding the support Serial Wire / JTAG port pins
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the following errors when sparse (SCA) is enabled:
soc/intel/intel_adsp/ace/power.c:46:12: warning:
cast removes address space '__cache' of expression
/soc/intel/intel_adsp/ace/power.c:48:9: warning:
incorrect type in argument 1 (different address spaces)
Fixes#70725
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Select the LPTIM clock source STM32_LPTIM_CLOCK to be
LSE or LSI depending on the DTS clocks property
of the stm32_lp_tick_source node.
This will also affect the SYS_CLOCK_TICKS_PER_SEC
depending on the lptim prescaler
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add SoC initialization to set the UART RDC permission in the early
phase, so that the it can be used by Zephyr on Cortex-A cores.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
To minimize time the CPU spends when preparing for sleep, make sure
the pending transactions are finished before calling `wfi`.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
The SOC name `imx8ulp` has been just a placeholder until
support for the SOC's ADSP (since this is the only core
that's supported in Zephyr) could be added to the NXP HAL.
Now that the support has been added, to make use of it, the
SOC name `imx8ulp` has to be changed to `mimx8ud7`. As such,
this commit does the following:
1) Introduces SOC part number configuration - needed
by some HAL headers.
2) Replaces all occurrences of `imx8ulp` (as the SOC
name) with `mimx8ud7`.
3) Enables `CONFIG_HAS_MCUX`.
4) Aligns all `CONFIG_SOC_` configurations with the
new SOC name.
5) Updates SOF hash. This is needed to fix build issues
caused by this name change. This is not done in a separate
commit to preserve bisectability.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Simple rename to align the kernel naming scheme. This is being
used throughout the tree, especially in the architecture code.
As this is not a private API internal to kernel, prefix it
appropriately with K_.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Doing a `GCLK->CTRLA.bit.SWRST = 1` will cause boot chaining to hang.
Setting the CPU clock to run from OSCULP32K during initialization is
all that is needed.
Signed-off-by: Jon Ringle <jringle@gridpoint.com>
Issue an upstream read transaction through uncached memory to flush
out all pending transactions before power down the host domain.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Fixes: #69785
The boards_legacy sub-folder was temporarily introduce in collab-hwm
branch during porting to HWMv2.
This should have been removed before merging collab-hwm to main as it
prevent looking up boards in oot roots.
Removing the temporary sub-folder for HWMv2.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Clean up early days TF-M development directives which are outdated today.
Factorize remaining CMake instructions in soc.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Replaces inaccurate or wrong vendor prefixes in board and soc
folder names with those from thr vendor prefix file
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Move the Kconfig symbols SOC_ESP32_PROCPU, SOC_ESP32_APPCPU,
SOC_ESP32S3_PROCPU, and SOC_ESP32S3_APPCPU.
The CPU cluster is defined in espessifc/soc.yml and should therefore
be available in the HWMv2 Kconfig.soc tree.
This will allow sysbuild to test for the CPU cluster when targeting
remote board for a build.
Update espressif boards accordingly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Interrupts should not be enabled this early in boot time.
Driver initializations expect IRQs not to arrive when
setting up HW.
Remove enabling `MSTATUS.MIE` in `__start`.
It will be enabled when main thread is switched to,
as threads by default start with enabled `MSTATUS.MIE`.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Due to HW issue, VPR needs to keep MSTATUS.MIE enabled during sleep.
Otherwise, interrupts will not wake it up.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
MEMC_MCUX_FLEXSPI depends on code relocation being enabled on parts that
XIP from the FlexSPI by default and requires a string describing the RAM
region to relocate code into. Add these Kconfigs to the RW SOC port.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch updates the power status register bitfield definitions in the
power management header for the Intel ADSP ACE 2.0 LNL platform.
Modifications include:
- Adjusting the 'ioxpgs' field from 4 bits to 2 bits.
- Adding a 'rsvd11' field with 2 bits to reflect reserved space.
- Changing the 'mlpgs' field from 2 bits to 1 bit.
- Updating the 'rsvd14' field from 1 bit to 2 bits for alignment.
These changes ensure that the power status register bitfields match the
latest hardware specification for the ACE 2.0 LNL SoC, which is crucial
for accurate power domain status monitoring.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
In the interrupt pending routine, only the interrupt status needs to be
cleared at the end of the interrupt routine. There is no need to do a
hardware reset(HALT) to avoid clearing the next transfer interrupt when
the current transfer is completed.
Test: Testing this function does not cause I2C data/clk to get stuck on
the system platform.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add support for propagating SOC_NRF54LX_DISABLE_FICR_TRIMCNF and
SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE values to nrfx.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
Previous adjustments to hwmv2 lost this Kconfig file.
Test: west build -p always -b it82xx2_evb samples/hello_world
config BOARD_IT82XX2_EVB
select SOC_IT82302_AX
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
When non-primary core is powered down and restart with sequence of:
- PM state set to SOFT_OFF
- once target core is idle, cut power with soc_adsp_halt_cpu()
- power up core again with k_smp_cpu_resume()
The execution will continue from stored DSP core context, but
will hit an assert in z_smp_cpu_mobile() as the PS.INTLEVEL
is zero.
Fix this issue by storing and restoring PS register in this flow.
Link: https://github.com/zephyrproject-rtos/zephyr/issues/70181
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The core clock of 8ULP's HIFI4 DSP runs at 475.2MHz. As such,
correct the value of `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` to
reflect this.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Transition to a low power DMI L1 state should be allowed only after all
pending DMA channels transfers have started.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Dependencies of NXP_IMXRT_BOOT_HEADER were set incorrectly for the
RT11xx series part when building a dual core image. The boot header
should be enabled by default for the primary M7 core, and always
disabled when MCUBOOT is used or the M4 core is targeted
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use `DT_REG_HAS_IDX()` instead of `DT_NODE_EXISTS()` when checking
if for a given nodelabel the base address of the associated node
should be validated, so that the validation is performed only if
the base address is available. This prevents build failures in cases
like the os_mgmt_datetime test where the `rtc` nodelabel is used for
an emulated RTC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Unlike the remainder of the RT10xx series, the RT1011 SOC requires that
the flash configuration block be placed at an offset of 0x400 bytes,
instead of the start of the flash.
Fixes#70090
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
With the transition to HWMv2, `CONFIG_CPU_HAS_DCACHE` is no
longer selected. This causes issues with Sound Open Firmware
since this configuration allows the usage of DCACHE-related
cache management operations. As such, to fix said issues,
select `CONFIG_CPU_HAS_DCACHE` on all NXP ADSP SOCs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Check the driver configuration to disable
the USB Type-C dead battery, only if
- a USB PD system is in place (the UCPD node is enabled)
- or the user does not require USB PHY anyway
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the core is not power gated, waiti will restore intlevel. In
this case we lock interruption after it.
In the bug scenario, the host starts streaming and via SOF APIs, keeps a
lock to prevent Zephyr from entering PM_STATE_RUNTIME_IDLE. During the
test case, host removes this block and core0 is allowed to enter IDLE
state.
When core0 enters power gated state, interrrupts are left enabled (so
the core can be woken up when something happens). This leaves a race
where suitably timed interrupt will actually block entry to power gated
state and k_cpu_idle() in power_gate_entry() will return. This is rare,
but happens often enough that the relatively short test plan run on SOF
pull-requests will trigger this case.
Fixes#69807
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The option SOC_NRF54L_GLITCHDET_WORKAROUND is not
needed anymore becuase the glitch detector is already
disabled in the Nordic MDK in the hal_nordic repo.
File path in hal_nordic:
nrfx/mdk/system_nrf54l.c
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Add entries for checking if the recently added dts nodes for nRF54H20
and nRF54L15 have correct base addresses (if they match those provided
by MDK).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Not all SOC cores within the NXP iMX RT family support power
management (for example, the Fusion F1 DSP has no support). Do not
select HAS_PM at the SOC family level, and instead select it at the
series level where applicable
Fixes#69731
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
While not needed when XIP=n, it can be still be selected so that come
defconfigs are simplified.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Running samples/subsys/ipc/openamp_rsc_table with some adjustments
sometimes results in linux kernel panics.
After experimenting it appears to be hit or miss depending on the
resource table alignment.
Explicitly aligning to 64bit (the native width), no more kernel panics
were seen.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
DCDC adjustment was enabled by default for RT11xx series before HWMv2
transition. Reenable it, as this is needed for some higher power
applications (such as display output)
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
z_mp_entry() and power_gate_exit() are only called from assembly code
in the same file, where they're defined. Make them "static" and add
an attribute to let the compiler know, that they aren't unused.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This enables the use of CONFIG_XTENSA_MORE_SPIN_RELAX_NOPS to
specify how many NOPs for arch_spin_relax(). This is to keep
the atomic_cas() (via s32c1i) from saturating the internal bus
with contant RCW ops. The numbers should be further tuned
for specific application but these should provide a good start.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Enabled the PIT and Multi channel support
for some of the rtXXXX devices.
- rt1010
- rt1060
- rt1160
- rt1170
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Update all usages of the MBOX API to the latest API changes (to be
squashed for bisectability).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Moved r8a77951/r8a77961 pfc tables and funcs from soc to drivers/pfc dir.
Move all Renesas pinctrl driver source and header files to a separate
directory "renesas" and every SoC series to a separate subdirectory.
Update the MAINTAINERS file to align with the changes in the
pinctrl directory.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Move pfc_r8a779f0.c from the 'soc' directory to the 'drivers'
directory to avoid code duplication for the ARM64 Spider board.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
SOC_TOOLCHAIN_NAME was used instead of the SoC name for setting include
path, so all SoCs were using the same path. Originally this was relying
on SoC (before hwmv2), so reverting back to using the SoC name instead
and renaming directories as well.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This was part of the mega hwmv2 commit. Looks like hpet drivers heavily
relies on soc.h. Reverting this for now while we look for a proper fix
and remove reliance on soc.h for drivers.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
During HWMv2 porting there was some build fails missed from
typos in the RT1064 and RT11XX series, fix these.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The finish interrupt after the previous transaction is completed may
occur in the next transaction. To do hardware reset at this time could
potentially lead to the failure of the transaction.
Therefore, removing the hardware reset upon completing the transaction
helps to avoid a race condition.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Commit a10fee2d5e (drivers: clock_control: ccm_rev2: add support for
reclocking FlexSPI) introduced the ability to set the FlexSPI
clock frequency at runtime on RT11xx series SOCs. However, this
implementation resulted in the clock frequency being rounded up, not
down. This can result in flash clock frequency violations on some
flash parts, causing the system to crash when running in XIP mode.
Fixes#69088
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When exiting PM_STATE_SOFT_OFF, the primary core state is always
used to restore bootctl register and the clock and power gating
settings.
This can lead to problems if non-primary core is powered up and down
many times before primary core 0 is powered down the first time.
The saved state in core_desc[0].bctl will be null, and as a result-
power gating and clock gating is not disabled correctly for
non-primary cores.
Link: https://github.com/thesofproject/sof/issues/8642
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Executing from RAM sections other than rom/code should cause a fault.
This is tested as part of the kernel mem_protect tests.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Add initial support for the VPR RISC-V core found in the new nRF54 SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Because both, RISC-V and ARM cores share the same pinctrl driver. The
top level common folder will disappear with the introduction of HWMv2,
where multi-arch SoCs will be well supported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Extend Kconfig definitions and nrfx_config translations so that UARTE
instances that are available in nRF54H20 can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
nrf-regtool is a Python utility from Nordic Semiconductor, which is used
for generating binary files with register values for given peripherals.
It sources the descriptions of peripheral registers from CMSIS-SVD files
(typically ones bundled with nRF MDK).
For some peripherals, such as UICR, nrf-regtool supports parsing values
from devicetree as well, based on the bindings already found in Zephyr.
Currently, this tool is not submitted as a script to Zephyr, but it can
be installed from PyPI.
Having nrf-regtool installed is recommended when working with nRF54H20.
Booting the Application or Radiocore CPU requires flashing not only its
firmware, but also its respective UICR instance. On this SoC, the UICR
is used to assign ownership of global hardware resources, including
memory and peripherals, to individual cores. The Zephyr build system can
call nrf-regtool to generate the UICR based on devicetree, to reflect
the boot-time hardware configuration required for a given application.
The generated `uicr.hex` is then merged with `zephyr.hex`, so that they
can be flashed together using west.
The build system integration takes the form of a CMake package, which
includes a version check and reusable components; over time, some of
these components can be reused by sysbuild. This package is located in
the `hal_nordic` module, because it depends on the `SOC_SVD_FILE` CMake
variable, which is defined there as well.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add nrfx and Kconfig related infrastructure plus SoC initialization
code to allow building for nRF54H20 targets (Application and Radio
cores).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... to cover missing __ICACHE_PRESENT and __DCACHE_PRESENT symbols that
should be defined in MDK files.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
GR716A has two SPIMCTRL SPI controllers.
This adds the SPIMCTRL description to the DTS and makes the SPI
option available in the kernel configuration.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Add support for reclocking flexspi in ccm_rev2 driver. Clock update
functions are provided for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Consistently use `zephyr_library*` cmake functions for all nRF Series
and set the Cortex-M linker script in a common place for all of them.
Remove no longer needed include directories.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In nRF54L15 FICR can be accessed also from non-secure code,
so it does not have NRF_FICR_S defined.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
NRF_RTC_TIMER will not be a default timer in the next
version of Nordic timer. It should be soc selection specific.
Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
The RA_PINCFG macro is used to generate a value that can be written
directly to the pin function select register. In addition to the pin
function this value also contains port and pin number information,
located in bit fields that are unused by the register. The bit field
used to store the port information consists of 3-bits. However, a typo in
the mask definition limited the field to two bits meaning only ports 0-3
could be configured. This patch resolves the issue, allowing ports 0-7 to
be configured. If the port is greater than 7 another field (port4) is used
to store an additional bit (allowing an additional 8 ports to be
supported). However, use of this field has not yet been implemented.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Adds CAN drivers for XMC4xxx SoCs.
XMC4xxx has multiple CAN nodes. The nodes share a common clock and
a message object pool.
The CAN nodes do not have a loopback mode. Instead there is an
internal bus which can be used to exchange messages between
nodes on the SoC. For this reason tests/samples which rely on the
loopback feature have been disabled.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
SOCFPGA_SYSMGR_REG_BASE base address now read from Device tree
This commit changes the way the SOCFPGA_SYSMGR_REG_BASE base address is
determined. Previously, the address was hard-coded in the system_manager
source file. This commit changes the code to read the address from the
Device tree. This makes the code more flexible and allows the base
address to be different for different boards.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
In pm_state_set we can't just call k_cpu_idle() because
this will clear out PS.INTLEVEL. Use k_cpu_atomic_idle instead
since Zephyr's expect interruptions to be locked after pm_state_set.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
We are arbitrarily setting a value to PS after power gates and
losing valid information like OWB, CALLINC and INTLEVEL.
We need to properly save/restore them to avoid possible wrong behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
ROM configures the ISP boot pins as gpio to determine what boot mode to
be in. But some ROM revisions have a bug where they do not restore the
reset state of these pins before booting application. This can cause
power leakage on these pins and is not an intended configuration from
Zephyr user/board point of view, so restore the reset state as part of
early SOC init (disable the pins). Configuration of pins should be
left up to app/board devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The OpenTitan PLIC has support for up to 255 interrupt vectors, so
set it to that. Previously was set to number of IRQs used.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
There is default 15K-ohm pull-down for USB controller.
To disable the default pull-down to avoid signal contention in GPIO mode.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
At chip startup, jtag pins are configured by default to enable
debug.
This configuration adds consumption and when using PM profile,
we can save ~40uA by resetting this configuration and setting pins
to analog mode.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Only when CONFIG_MP_MAX_NUM_CPUS > 1, then .bss is put in
uncached region. Otherwise, .bss is in cached region.
So the assertion that g_key_read_holder must be in uncached
region must take into account how many CPUs are enabled on
build.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Commit 3b99fb1b4a ("xtensa: do not imply atomic ops kconfig") removed
ATOMIC_OPERATIONS_ARCH at xtensa arch level. This triggers a bug in
intel_adsp cavs builds with XCC compiler as
CONFIG_ATOMIC_OPERATIONS_BUILTIN is not defined but neither is
CONFIG_ATOMIC_OPERATIONS_ARCH anymore, resulting in failed builds.
Fix the XCC build by defining CONFIG_ATOMIC_OPERATIONS_ARCH at
soc level.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
This allows to link code and data blocks, e.g. the vector table, into
tightly coupled memory using `zephyr_linker_sources`.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
When set, this GPIO controller has pins associated with the
keyboard controller. In this case the reg_gpcr property is
overloaded and used to write the keyboard GCTRL register
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Updated the files present in device_init, hfxo_manager, power_manager
and sleeptimer folder as per latest version of gecko_sdk.
Added SL_DEVICE_INIT_HFXO_PRECISION in sl_device_init_hfxo_config.
Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
With the introduction of the SAI and EDMA drivers, there's
no longer a need to map the MMIOs using the mmu_regions.c
method since this is taken care of by the drivers via
device_map(). As such, remove entries for EDMA and SAI from
mmu_regions.c.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
It looks like all SoCs in tree check if an exception comes from an IRQ
the same way, so let's provide a common logic by default, still
customizable if the SoC selects RISCV_SOC_ISR_CHECK.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
use CONFIG_SOC_INTEL_ACE15_MTPM instead of CONFIG_ACE_VERSION_1_5.
CONFIG_ACE_VERSION_1_5 leaked from SOF.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add functions to Atmel SAM SoC PMC API. This is an effort to hide
most of the internal registers used in different SAM families.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The clock z_arm_platform_init hangs switching between clocks when using
MCUboot. This fixes the issue using the 8MHz internal clock as gclk_main
source when configuring PLL/DFLL.
Fixes: #67220
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The HAS_SPI_DW Kconfig is rather unncessary. If the synopsys designware
spi is to be included. It should come from the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Some definitions were only used in soc.c, there's no need to expose them
in a public header like soc.h.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
<soc.h> is needed to pull some APIs defined in soc.h.
<fsl_device_registers.h> is needed to access EVENT0/1 addresses.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
