Commit graph

3813 commits

Author SHA1 Message Date
Eugeniy Paltsev
9cb9906418 ARC: cleanup exit_tickless_idle
Rewrite 'exit_tickless_idle' macro to make code more readable.
No functional changes intended.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-07-24 12:05:12 +02:00
Eugeniy Paltsev
3f544ca5b2 ARC: replace NOP ASM inlines with builtin
NOP instruction is available via builtin for ARC so get rid of all
ASM inlines with NOP/NOP_S instructions.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-07-24 12:05:12 +02:00
Andrzej Głąbek
ec8cb07da2 arch: arm: Export vector table symbols with GDATA instead of GTEXT
_vector_table and __vector_relay_table symbols were exported with GTEXT
(i.e. as functions). That resulted in bit[0] being incorrectly set in
the addresses they represent (for functions this bit set to 1 specifies
execution in Thumb state).
This commit corrects this by switching to exporting these objects as
objects, i.e. with GDATA.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-07-24 12:04:28 +02:00
Daniel Leung
3f6ac9fdfd arm: add include guard for offset files
MISRA-C directive 4.10 requires that files being included must
prevent itself from being included more than once. So add
include guards to the offset files, even though they are C
source files.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-07-24 10:01:12 +02:00
Daniel Leung
49199641b9 x86: add include guard for offset files
MISRA-C directive 4.10 requires that files being included must
prevent itself from being included more than once. So add
include guards to the offset files, even though they are C
source files.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-07-24 10:01:12 +02:00
David Leach
5803ec1bf0 arch: arm: mpu: Use temporary MPU mapping while reprogramming NXP MPU
Race conditions exist when remapping the NXP MPU. When writing the
start, end, or attribute registers of a MPU descriptor, the hardware
will automatically clear the region's valid bit. If that region gets
accessed before the code is able to set the valid bit, the core will
fault.

Issue #20595 revealled this problem with the code in region_init()
when the compiler options are set to no optimizations. The code
generated by the compiler put local variables on the stack and then
read those stack based variables when writing the MPU descriptor
registers. If that region mapped the stack a memory fault would occur.
Higher compiler optimizations would store these local variables in
CPU registers which avoided the memory access when programming the
MPU descriptor.

Because the NXP MPU uses a logic OR operation of the MPU descriptors,
the fix uses the last descriptor in the MPU hardware to remap all of
dynamic memory for access instead of the first of the dynamic memory
descriptors as was occuring before. This allows reprogramming of the
primary discriptor blocks without having a memory fault. After all
the dynamic memory blocks are mapped, the unused blocks will have
their valid bits cleared including this temporary one, if it wasn't
alread changed during the mapping of the current set.

Fixes #20595

Signed-off-by: David Leach <david.leach@nxp.com>
2020-07-22 11:27:40 +02:00
Eugeniy Paltsev
3eee762e08 ARC: NSIM: switch to ns16550 UART model
Switch nSIM from custom ARC UART to ns16550 model. That will
allow us to use zephyr images built for nSIM on other platforms
like HAPS, QEMU, etc...

This patch do:
 * switch nSIM board to ns16550 UART usage
 * change nSIM simulator configuration to use ns16550 UART model
 * drop checks for CONFIG_UART_NSIM in ARC code
 * update nSIM documentation

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-07-20 13:34:34 -04:00
Andrew Boie
98bcc51b09 x86: gen_gdt: improve docstring
Describe what info we're snarfing out of the prebuilt kernel.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-19 08:50:52 -04:00
Johan Hedberg
38333afe0e arch: x86: zefi: Reduce data section alignment requirement from 8 to 4
It's not safe to assume that the data section is 8-byte aligned.
Assuming 4-byte alignment seems to work however, and results in
simpler code than arbitrary alignment support.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-07-18 08:44:31 -04:00
Anas Nashif
4382532fd3 x86: zefi: support arguments and make compatible with windows
Add argument parsing and use os.path.join where possible to support
building on windows.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-07-18 08:44:31 -04:00
Andrew Boie
4df734683e x86: 32-bit: enable thread stack info
The hardware stack overflow feature requires
CONFIG_THREAD_STACK_INFO enabled in order to distingush
stack overflows from other causes when we get an exception.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-18 07:21:53 -04:00
Andrew Boie
aec607cc67 x86: remove memory mapping SOC code
This isn't needed any more, all of these directives were
for drivers which use device_map() now.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
c802cc8920 x86: pcie: use device_map() for MMIO config access
Replaces custom runtime calls to map memory.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
ee3c50ba6d x86: apic: use device MMIO APIs
A hack was required for the loapic code due to the address
range not being in DTS. A bug was filed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
a810c7b5a0 x86: early_serial: use device_map()
This driver code uses PCIe and doesn't use Zephyr's
device model, so we can't use the nice DEVICE_MMIO macros.
Set stuff up manually instead using device_map().

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
e7376057ca x86: add arch_mem_map()
This currently only supports identity paging; there's just
enough here for device_map() calls to work.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
542dcae0c7 arch: add CONFIG_MMU
This config indicates that a memory management unit is present
and enabled, which will in turn allow arch APIs to allow
mapping memory to be used.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
ff294e02cd arch: add CONFIG_CPU_HAS_MMU
Indicate that the CPU has a memory management unit,
similar to CPU_HAS_MPU for MPUs.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Aastha Grover
ffd8e8aefc arch: x86: core: Add cache flush function for x86
Adding just the cache flush function for x86. The name
arch_cache_flush comply with API names in include/cache.h

Signed-off-by: Aastha Grover <aastha.grover@intel.com>
2020-07-15 15:53:26 -07:00
Aastha Grover
97ecad69f0 include: Implement API's for cache flush and cache invalidate
arch: arc: core: Add Cache Implementation function & prototype for arc

Signed-off-by: Aastha Grover <aastha.grover@intel.com>
2020-07-15 15:53:26 -07:00
Johan Hedberg
0329027bd8 arch: x86: zefi: Fix assuming segment size being a multiple of 8
The p_memsz field which indicates the size of a segment in memory
isn't always a multiple of 8. Remove the assert and add padding if
necessary. Without this change it's not possible to generate EFI
binaries out of all samples & tests in the tree.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-07-14 18:21:38 -04:00
Rafał Kuźnia
f2b0bfda8f arch: arm: aarch32: Always use VTOR when it is available
Zephyr applications will always use the VTOR register when it is
available on the CPU and the register will always be configured
to point to applications vector table during startup.

SW_VECTOR_RELAY_CLIENT is meant to be used only on baseline ARM cores.

SW_VECTOR_RELAY is intended to be used only by the bootloader.
The bootloader may configure the VTOR to point to the relay table
right before chain-loading the application.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2020-07-14 16:17:30 +02:00
Andrzej Puzdrowski
4152ccf124 arch/arm/aarch32: ensured SW IRQ relay modes exclusive
Select either SW_VECTOR_RELAY or SW_VECTOR_RELAY_CLIENT
at the time.

Removed #ifdef-ry in irq_relay.S as SW_VECTOR_RELAY was
refined so it became reserved for the bootloader and it
conditionally includes irq_relay.S for compilation.
See SHA #fde3116f1981cf152aadc2266c66f8687ea9f764

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2020-07-14 16:17:30 +02:00
Rafał Kuźnia
89bf746ebe arch/arm/aarch32: add IRQ relay mechanism to ARMv7/8-M
This patch allows the `SW_VECTOR_RELAY` and
`SW_VECTOR_RELAY_CLIENT` pair to be
enabled on the ARMv7-M and ARMv8-M architectures
and covers all additional interrupt vectors.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2020-07-14 16:17:30 +02:00
Ioannis Glaropoulos
e80e655b01 arch: arm: cortex_m: align vector table based on VTOR requirements
Enforce VTOR table offset alignment requirements on Cortex-M
vector table start address.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-07-14 13:03:25 +02:00
Karsten Koenig
2e61137cc9 arch: riscv: thread: Init soc context on stack
The optional SOC_CONTEXT carries processor state registers that need to
be initialized properly to avoid uninitialized memory read as processor
state.
In particular on the RV32M1 the extra soc context stores a state for
special loop instructions, and loading non zero values will have the
core assume it is in a loop.

Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2020-07-13 15:00:19 -05:00
Stephanos Ioannidis
3322489d22 config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET
The `TEXT_SECTION_OFFSET` symbol is used to specify the offset between
the beginning of the ROM area and the address of the first ROM section.

This commit renames `TEXT_SECTION_OFFSET` to `ROM_START_OFFSET` because
the first ROM section is not always the `.text` section.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-07-09 14:02:38 -04:00
Andy Ross
0e20eafe7a arch/x86: Make sure PCI mmio is initialized before page tables
The page table initialization needs a populated PCI MMIO
configuration, and that is lazy-evaluated.  We aren't guaranteed that
a driver already hit that path, so be sure to call it explicitly.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-07-08 12:34:09 +02:00
Andy Ross
2626d702c6 arch/x86: zefi must disable HPET before OS handoff
The firmware on existing devices uses HPET timer zero for its own
purposes, and leaves it alive with interrupts enabled.  The Zephyr
driver now knows how to recover from this state with fuller
initialization, but that's not enough to fix the inherent race:

The timer can fire BEFORE the driver initialization happens (and does,
with certain versions of the EFI shell), thus flagging an interrupt to
what Zephyr sees as a garbage vector.  The OS can't fix this on its
own, the EFI bootloader (which is running with interrupts enabled as
part of the EFI environment) has to do it.  Here we can know that our
setting got there in time and didn't result in a stale interrupt flag
in the APIC waiting to blow up when interrupts get enabled.

Note: this is really just a workaround.  It assumes the hardware has
an HPET with a standard address.  Ideally we'd be able to build zefi
using Zephyr kconfig and devicetree values and predicate the HPET
reset on the correct configuraiton.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-07-08 12:34:09 +02:00
Andy Ross
c7d76cbe58 arch/x86: Add a spurious interrupt handler to x86_64
Right now x86_64 doesn't install handlers for vectors that aren't
populated by Zephyr code.  Add a tiny spurious interrupt handler that
logs the error and triggers a fatal error, like other platforms do.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-07-08 12:34:09 +02:00
Andy Ross
f7dd9856ba arch/x86/early_serial: General code cleanup
This patch is almost entirely aesthetics, designed to isolate the
variant configurations to a simple macro API (just IN/OUT), reduce
complexity derived from code pasted out of the larger ns16550 driver,
and keep the complexity out of the (very simple!) core code.  Useful
when hacking on the driver in contexts where it isn't working yet.

The sole behavioral change here is that I've removed the runtime
printk hook installation in favor of defining an
arch_printk_char_out() function which overrides the weak-linked
default (that is, we don't need to install a hook, we can be the
default hook at startup).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-07-08 12:34:09 +02:00
Andy Ross
d2eca354e8 arch/x86: early_serial cleanup
Various cleanups to the x86 early serial driver, mostly with the goal
of simplifying its deployment during board bringup (which is really
the only reason it exists in the first place):

+ Configure it =y by default.  While there are surely constrained
  environments that will want to disable it, this is a TINY driver,
  and it serves a very important role for niche tasks.  It should be
  built always to make sure it works everywhere.

+ Decouple from devicetree as much as possible.  This code HAS to work
  during board bringup, often with configurations cribbed from other
  machines, before proper configuration gets written.  Experimentally,
  devicetree errors tend to be easy to make, and without a working
  console impossible to diagnose.  Specify the device via integer
  constants in soc.h (in the case of IOPORT access, we already had
  such a symbol) so that the path from what the developer intends to
  what the code executes is as short and obvious as possible.
  Unfortunately I'm not allowed to remove devicetree entirely here,
  but at least a developer adding a new platform will be able to
  override it in an obvious way instead of banging blindly on the
  other side of a DTS compiler.

+ Don't try to probe the PCI device by ID to "verify".  While this
  sounds like a good idea, in practice it's just an extra thing to get
  wrong.  If we bail on our early console because someone (yes, that's
  me) got the bus/device/function right but typoed the VID/DID
  numbers, we're doing no one any favors.

+ Remove the word-sized-I/O feature.  This is a x86 driver for a PCI
  device.  No known PC hardware requires that UART register access be
  done in dword units (in fact doing so would be a violation of the
  PCI specifciation as I understand it).  It looks to have been cut
  and pasted from the ns16550 driver, remove.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-07-08 12:34:09 +02:00
Andy Ross
36b8db0129 arch/x86: Map 512G by default when booting x86_64
The default page table (the architecturally required one used for
entrance to long mode, before the OS page tables get assembled) was
mapping the first 4G of memory.

Extend this to 512G by fully populating the second level page table.
We have devices now (up_squared) which have real RAM mapped above 4G.
There's really no good reason not to do this, the page is present
always anyway.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-07-08 12:34:09 +02:00
Andy Ross
4d5e67ed13 arch/x86: Unbreak SMP startup on x86_64
A last minute "cleanup" to the EFI startup path (on a system where I
had SMP disabled) moved the load of the x86_cpuboot[0] entry into RBP
into the main startup code, which is wrong because on auxiliary CPUs
that's already set up by the 16/32 bit entry code to point to the
OTHER entries.

Put it back where it belongs.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-07-07 12:59:33 -04:00
Watson Zeng
85acfd2e27 arch: arc: irq: bugs fix for fast irq in one register bank config
* The stack pointer (SP) register points to the lowest-used address of
   a downward-growing stack, so memory address [sp] is used, we can't
   modify it.

* In firq_no_switch case, we need to pop sp, which pushed before
   _isr_demux function in firq_nest function.

Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
2020-07-07 15:10:26 +02:00
Ioannis Glaropoulos
fde3116f19 arch: arm: cortex_m: Add config for SW_VECTOR_RELAY_CLIENT
Define vector relay tables for bootloader only.
If an image is not a bootloader image (such as an MCUboot image)
but it is a standard Zephyr firmware, chain-loadable by a
bootloader, then this image will not need to relay IRQs itself.
In this case SW_VECTOR_RELAY_CLIENT should be used to setting the
vector table pointer in RAM so the parent image can forward the
interrupts to it.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Co-authored-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2020-07-03 13:34:50 -04:00
Andy Ross
928d31125f arch/x86: Add zefi, an EFI stub/packer/wrappper/loader
This is a first cut on a tool that will convert a built Zephyr ELF
file into an EFI applciation suitable for launching directly from the
firmware of a UEFI-capable device, without the need for an external
bootloader.

It works by including the Zephyr sections into the EFI binary as
blobs, then copying them into place on startup.

Currently, it is not integrated in the build.  Right now you have to
build an image for your target (up_squared has been tested) and then
pass the resulting zephyr.elf file as an argument to the
arch/x86/zefi/zefi.py script.  It will produce a "zephyr.efi" file in
the current directory.

This involved a little surgery in x86_64 to copy over some setup that
was previously being done in 32 bit mode to a new EFI entry point.
There is no support for 32 bit UEFI targets for toolchain reasons.

See the README for more details.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-07-02 09:10:01 -04:00
Andy Ross
7c6d8aa58e arch/x86: Add support for PCI MMIO configuration access
The traditional IO Port configuration mechanism was technically
deprecated about 15 years ago when PCI Express started shipping.
While frankly the MMIO support is significantly more complicated and
no more performant in practice, Zephyr should have support for current
standards.  And (particularly complicated) devices do exist in the
wild whose extended capability pointers spill beyond the 256 byte area
allowed by the legacy mechanism.  Zephyr will want drivers for those
some day.

Also, Windows and Linux use MMIO access, which means that's what
system vendors validate.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-06-23 13:07:39 +02:00
Andy Ross
7fe8caebc0 arch/x86: Add z_acpi_find_table(), MCFG support
The existing minimal ACPI implementation was enough to find the MADT
table for dumping CPU info.  Enhance it with a slightly less minimal
implementation that can fetch any table, supports the ACPI 2.0 XSDT
directory (technically required on 64 bit systems so tables can live
>4G) and provides definitions for the MCFG table with the PCI
configuration pointers.

Note that there is no use case right now for high performance table
searching, so the "init" step has been removed and tables are probed
independently from scratch for each one requested (there are only
two).

Note also that the memory to which these tables point is not
understood by the Zephyr MMU configuration, so in long mode all ACPI
calls have to be done very early, before z_x86_paging_init() (or on a
build with the MMU initialization disabled).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-06-23 13:07:39 +02:00
Andrew Boie
a8585ac35c x86: fix early boot pagefault reason code
If we get a page fault in early boot context, before
main thread is started, page faults were being
incorrectly reported as stack overflows.
z_x86_check_stack_bounds() needs to consider the
interrupt stack as the correct stack for this context.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-18 19:36:17 +02:00
Andrew Boie
87dd0492db x86: add CONFIG_X86_KERNEL_OFFSET
Previously, DTS specification of physical RAM bounds did not
correspond to the actual bounds of system RAM as the first
megabyte was being skipped.

There were reasons for this - the first 1MB on PC-like systems
is a no-man's-land of reserved memory regions, but we need DTS
to accurately capture physical memory bounds.

Instead, we introduce a config option which can apply an offset
to the beginning of physical memory, and apply this to the "RAM"
region defined in the linker scripts.

This also fixes a problem where an extra megabyte was being
added to the size of system RAM.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-18 19:35:52 +02:00
Scott Branden
d77fbcb86a arch: arm64: mmu: create macro for TCR_PS_BITS
Create macro for TCR_PS_BITS instead of programmatically looking up
a static value based on a CONFIG option.  Moving to macro
removes logically dead code reported by Coverity static analysis tool.

Signed-off-by: Scott Branden <scott.branden@broadcom.com>
2020-06-18 12:47:30 +02:00
Andrew Boie
8920549464 qemu_x86: propagate exit reason code to the shell
This helps distingush between fatal errors if logging isn't
enabled.

As detailed in comments, pass a reason code which controls
the QEMU process' return value.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-12 23:24:37 -04:00
Andrew Boie
bed6b6891d x86: report when thread re-use is detected
x86_64's __resume path 'poisons' the incoming thread's
saved RIP value with a special 0xB9 value, to catch
re-use of thread objects across CPUs in SMP. Add a check
and printout for this when handling fatal errors, and
treat as a kernel panic.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-10 18:36:06 -04:00
Andrew Boie
faff50d8e7 arc: show all registers on exception
The ESF contains register file contents including program
counter when the exception happened. If non-NULL and we
have ARC_EXCEPTION_DEBUG enabled, dump its contents to the
log stream.

Other arches do this already.

There is no need to read ERET, the ESF already contains the
interrupted PC value.

A future enhancement could create an option to additionally
push callee-saved register context into the ESF so it can
also be dumped out, but this patch does not address this.

A future enhancement could also convert the syscall
stack frame pointer passed to arch_syscall_oops() into
an ESF so that context of the failed system call can be
inferred.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-09 13:52:56 +02:00
Rubin Gerritsen
3cf7f9c974 arch: posix: Print warning on sys_reboot
This will simplify debugging.

Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
2020-06-09 08:19:50 +02:00
Kumar Gala
a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Ioannis Glaropoulos
9d8111c88f arch: arm: cortex-m: fix placement of ARMv7-M-related MPU workaround
The workaround for ARMv7-M architecture (which proactively
decreases the available thread stack by the size of the MPU
guard) needs to be placed before we calculate the pointer of
the user-space local thread data, otherwise this pointer will
fall beyond the boundary of the thread stack area.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-05-27 19:48:27 +02:00
Ioannis Glaropoulos
6b54958a0e arch: arm: aarch32: cortex-m: fix logic for detecting guard violation
We fix (by inverting) the logic of the IS_MPU_GUARD_VIOLATION
macro, with respect to the value of the supplied 'fault_addr'.
We shall only be inspecting the fault_addr value if it is not
set to -EINVAL.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-05-27 10:10:22 +02:00
Ioannis Glaropoulos
7284aee7d7 arch: arm: aarch32: cortex_m: add note in mem_manage_fault()
It is possible that MMFAR address is not written by the
Cortex-M core; this occurs when the stacking error is
not accompanied by a data access violation error (i.e.
when stack overflows due to the exception entry frame
stacking): z_check_thread_stack_fail() shall be able to
handle the case of 'mmfar' holding the -EINVAL value.

Add this node in mem_manage_fault() function to clarify
that it is valid for z_check_thread_stack_fail() to be
called with invalid mmfar address value.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-05-27 10:10:22 +02:00