arch/x86/early_serial: General code cleanup
This patch is almost entirely aesthetics, designed to isolate the variant configurations to a simple macro API (just IN/OUT), reduce complexity derived from code pasted out of the larger ns16550 driver, and keep the complexity out of the (very simple!) core code. Useful when hacking on the driver in contexts where it isn't working yet. The sole behavioral change here is that I've removed the runtime printk hook installation in favor of defining an arch_printk_char_out() function which overrides the weak-linked default (that is, we don't need to install a hook, we can be the default hook at startup). Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross
Carles Cufí
parent
d2eca354e8
commit
f7dd9856ba
1 changed files with 54 additions and 77 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018 Intel Corporation
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -7,78 +7,61 @@
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#include <kernel.h>
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#include <sys/util.h>
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#include <drivers/pcie/pcie.h>
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#include <soc.h>
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#if defined(X86_SOC_EARLY_SERIAL_PCIDEV)
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#define UART_PCIE_BDF X86_SOC_EARLY_SERIAL_PCIDEV
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#define UART_NS16550_PCIE_ENABLED 1
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#elif defined(UART_NS16550_ACCESS_IOPORT)
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#undef UART_NS16550_PCIE_ENABLED
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#else
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#error "Incomplete x86 SoC early serial config"
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#endif
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/* Super-primitive 8250/16550 serial output-only driver, 115200 8n1 */
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#define REG_OFFSET_THR 0x00 /* Transmitter holding reg. */
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#define REG_OFFSET_IER 0x01 /* Interrupt enable reg. */
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#define REG_OFFSET_FCR 0x02 /* FIFO control reg. */
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#define REG_OFFSET_LCR 0x03 /* Line control reg. */
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#define REG_OFFSET_MCR 0x04 /* Modem control reg. */
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#define REG_OFFSET_LSR 0x05 /* Line status reg. */
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#define REG_OFFSET_BRDL 0x00 /* Baud rate divisor (LSB) */
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#define REG_OFFSET_BRDH 0x01 /* Baud rate divisor (MSB) */
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#define IER_DISABLE 0x00
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#define LCR_8N1 (BIT(0) | BIT(1))
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#define LCR_DLAB_SELECT BIT(7)
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#define MCR_DTR BIT(0)
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#define MCR_RTS BIT(1)
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#define LSR_THRE BIT(5)
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#define FCR_FIFO BIT(0) /* enable XMIT and RCVR FIFO */
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#define FCR_RCVRCLR BIT(1) /* clear RCVR FIFO */
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#define FCR_XMITCLR BIT(2) /* clear XMIT FIFO */
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#define FCR_FIFO_1 0 /* 1 byte in RCVR FIFO */
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/* convenience defines */
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#define REG_THR(x) (x + REG_OFFSET_THR * UART_REG_ADDR_INTERVAL)
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#define REG_IER(x) (x + REG_OFFSET_IER * UART_REG_ADDR_INTERVAL)
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#define REG_FCR(x) (x + REG_OFFSET_FCR * UART_REG_ADDR_INTERVAL)
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#define REG_LCR(x) (x + REG_OFFSET_LCR * UART_REG_ADDR_INTERVAL)
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#define REG_MCR(x) (x + REG_OFFSET_MCR * UART_REG_ADDR_INTERVAL)
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#define REG_LSR(x) (x + REG_OFFSET_LSR * UART_REG_ADDR_INTERVAL)
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#define REG_BRDL(x) (x + REG_OFFSET_BRDL * UART_REG_ADDR_INTERVAL)
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#define REG_BRDH(x) (x + REG_OFFSET_BRDH * UART_REG_ADDR_INTERVAL)
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/* Legacy I/O Port Access to a NS16550 UART */
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#ifdef UART_NS16550_ACCESS_IOPORT
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#define INBYTE(x) sys_in8(x)
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#define OUTBYTE(x, d) sys_out8(d, x)
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#ifndef UART_REG_ADDR_INTERVAL
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#define UART_REG_ADDR_INTERVAL 1 /* address diff of adjacent regs. */
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#endif /* UART_REG_ADDR_INTERVAL */
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#else
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#define INBYTE(x) sys_read8(x)
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#define OUTBYTE(x, d) sys_write8(d, x)
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#ifndef UART_REG_ADDR_INTERVAL
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#define UART_REG_ADDR_INTERVAL 4 /* address diff of adjacent regs. */
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#define IN(reg) sys_in8(reg + UART_NS16550_ACCESS_IOPORT)
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#define OUT(reg, val) sys_out8(val, reg + UART_NS16550_ACCESS_IOPORT)
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#endif
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#endif /* UART_NS16550_ACCESS_IOPORT */
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#ifdef UART_NS16550_PCIE_ENABLED
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static mm_reg_t base;
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#else
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#define base PORT
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/* "Modern" mapping of a UART into a PCI MMIO device. The registers
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* are still bytes, but spaced at a 32 bit stride instead of packed
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* together.
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*/
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#ifdef X86_SOC_EARLY_SERIAL_PCIDEV
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static uintptr_t pci_bar;
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#define IN(reg) (sys_read32(pci_bar + reg * 4) & 0xff)
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#define OUT(reg, val) sys_write32((val) & 0xff, pci_bar + reg * 4)
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#endif
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/* Still other devices use a MMIO region containing packed byte
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* registers
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*/
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#ifdef X86_SOC_EARLY_SERIAL_MMIO8_ADDR
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#define IN(reg) sys_read8(X86_SOC_EARLY_SERIAL_MMIO8_ADDR + reg)
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#define OUT(reg, val) sys_write8(val, X86_SOC_EARLY_SERIAL_MMIO8_ADDR + reg)
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#endif
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#define REG_THR 0x00 /* Transmitter holding reg. */
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#define REG_IER 0x01 /* Interrupt enable reg. */
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#define REG_FCR 0x02 /* FIFO control reg. */
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#define REG_LCR 0x03 /* Line control reg. */
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#define REG_MCR 0x04 /* Modem control reg. */
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#define REG_LSR 0x05 /* Line status reg. */
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#define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
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#define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
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#define IER_DISABLE 0x00
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#define LCR_8N1 (BIT(0) | BIT(1))
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#define LCR_DLAB_SELECT BIT(7)
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#define MCR_DTR BIT(0)
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#define MCR_RTS BIT(1)
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#define LSR_THRE BIT(5)
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#define FCR_FIFO BIT(0) /* enable XMIT and RCVR FIFO */
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#define FCR_RCVRCLR BIT(1) /* clear RCVR FIFO */
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#define FCR_XMITCLR BIT(2) /* clear XMIT FIFO */
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#define FCR_FIFO_1 0 /* 1 byte in RCVR FIFO */
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static void serout(int c)
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{
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while ((INBYTE(REG_LSR(base)) & LSR_THRE) == 0) {
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while ((IN(REG_LSR) & LSR_THRE) == 0) {
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}
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OUTBYTE(REG_THR(base), c);
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OUT(REG_THR, c);
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}
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static int console_out(int c)
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int arch_printk_char_out(int c)
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{
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if (c == '\n') {
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serout('\r');
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@ -87,26 +70,20 @@ static int console_out(int c)
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return c;
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}
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extern void __printk_hook_install(int (*fn)(int));
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void z_x86_early_serial_init(void)
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{
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#ifdef UART_NS16550_PCIE_ENABLED
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base = pcie_get_mbar(UART_PCIE_BDF, 0);
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pcie_set_cmd(UART_PCIE_BDF, PCIE_CONF_CMDSTAT_MEM, true);
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#ifdef X86_SOC_EARLY_SERIAL_PCIDEV
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pci_bar = pcie_get_mbar(X86_SOC_EARLY_SERIAL_PCIDEV, 0);
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pcie_set_cmd(X86_SOC_EARLY_SERIAL_PCIDEV, PCIE_CONF_CMDSTAT_MEM, true);
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#endif
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OUTBYTE(REG_IER(base), IER_DISABLE); /* Disable interrupts */
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OUTBYTE(REG_LCR(base), LCR_DLAB_SELECT);/* DLAB select */
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OUTBYTE(REG_BRDL(base), 1); /* Baud divisor = 1 */
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OUTBYTE(REG_BRDH(base), 0);
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OUTBYTE(REG_LCR(base), LCR_8N1); /* LCR = 8n1 + DLAB off */
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OUTBYTE(REG_MCR(base), MCR_DTR | MCR_RTS);
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OUT(REG_IER, IER_DISABLE); /* Disable interrupts */
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OUT(REG_LCR, LCR_DLAB_SELECT); /* DLAB select */
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OUT(REG_BRDL, 1); /* Baud divisor = 1 */
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OUT(REG_BRDH, 0);
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OUT(REG_LCR, LCR_8N1); /* LCR = 8n1 + DLAB off */
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OUT(REG_MCR, MCR_DTR | MCR_RTS);
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/* Turn on FIFO. Some hardware needs this before transmitting */
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OUTBYTE(REG_FCR(base),
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FCR_FIFO | FCR_FIFO_1 | FCR_RCVRCLR | FCR_XMITCLR);
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/* Will be replaced later when a real serial driver comes up */
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__printk_hook_install(console_out);
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OUT(REG_FCR, FCR_FIFO | FCR_FIFO_1 | FCR_RCVRCLR | FCR_XMITCLR);
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}
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