arch/arm/aarch32: add IRQ relay mechanism to ARMv7/8-M
This patch allows the `SW_VECTOR_RELAY` and `SW_VECTOR_RELAY_CLIENT` pair to be enabled on the ARMv7-M and ARMv8-M architectures and covers all additional interrupt vectors. Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no> Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
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5 changed files with 36 additions and 54 deletions
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@ -21,7 +21,7 @@ zephyr_library_sources(
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zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
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zephyr_library_sources_ifdef(CONFIG_CPLUSPLUS __aeabi_atexit.c)
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zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
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zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M0 irq_relay.S)
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zephyr_library_sources_ifdef(CONFIG_SW_VECTOR_RELAY irq_relay.S)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
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add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)
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@ -267,21 +267,16 @@ config DYNAMIC_DIRECT_INTERRUPTS
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config SW_VECTOR_RELAY
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bool "Enable Software Vector Relay"
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depends on ARMV6_M_ARMV8_M_BASELINE && !(CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP || CPU_CORTEX_M_HAS_VTOR)
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help
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When building bootloader firmware this option adds a
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Vector Table relay handler and relay vector table, to
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When building a bootloader firmware this option adds a
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vector table relay handler and a vector relay table, to
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relay interrupts based on a vector table pointer.
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This is only
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required for Cortex-M0 (or an Armv8-M baseline core) with no hardware
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vector table relocation mechanisms or for Cortex-M0+
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(or an Armv8-M baseline core) with no VTOR and no other hardware
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relocation table mechanisms.
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This is only required but not limited to Cortex-M Baseline CPUs
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with no hardware vector table relocation mechanisms (e.g. VTOR).
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config SW_VECTOR_RELAY_CLIENT
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bool "Enable Software Vector Relay (client)"
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default y if BOOTLOADER_MCUBOOT
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depends on ARMV6_M_ARMV8_M_BASELINE && !(CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP || CPU_CORTEX_M_HAS_VTOR)
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default y if BOOTLOADER_MCUBOOT && !(CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP || CPU_CORTEX_M_HAS_VTOR)
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help
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Another image has enabled SW_VECTOR_RELAY, and will relay interrupts
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to this image. Enable this to make sure the vector table pointer in
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@ -75,37 +75,10 @@ SECTION_FUNC(vector_relay_table, __vector_relay_table)
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.word __vector_relay_handler
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/* End of system exception */
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.rept CONFIG_NUM_IRQS
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.word __vector_relay_handler
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.endr
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GTEXT(__vector_relay_table)
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#endif
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@ -40,28 +40,39 @@
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#ifdef CONFIG_CPU_CORTEX_M_HAS_VTOR
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#ifdef CONFIG_XIP
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#ifdef CONFIG_SW_VECTOR_RELAY
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#define VECTOR_ADDRESS ((uintptr_t)__vector_relay_table)
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#else
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#define VECTOR_ADDRESS ((uintptr_t)_vector_start)
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#else
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#define VECTOR_ADDRESS CONFIG_SRAM_BASE_ADDRESS
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#endif
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static inline void relocate_vector_table(void)
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{
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SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
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__DSB();
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__ISB();
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}
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#else /* CONFIG_XIP */
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#define VECTOR_ADDRESS CONFIG_SRAM_BASE_ADDRESS
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#endif /* CONFIG_XIP */
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#else
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#else /* CONFIG_CPU_CORTEX_M_HAS_VTOR */
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#define VECTOR_ADDRESS 0
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#endif /* CONFIG_CPU_CORTEX_M_HAS_VTOR */
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#if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
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Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used))
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void *_vector_table_pointer;
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#endif
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#define VECTOR_ADDRESS 0
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#ifdef CONFIG_CPU_CORTEX_M_HAS_VTOR
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static inline void relocate_vector_table(void)
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#else
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void __weak relocate_vector_table(void)
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#endif
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{
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#if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR) && !defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
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SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
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__DSB();
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__ISB();
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#endif
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#if !defined(CONFIG_CPU_CORTEX_M_HAS_VTOR) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
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#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
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!defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
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size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
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@ -69,14 +80,13 @@ void __weak relocate_vector_table(void)
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#elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
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_vector_table_pointer = _vector_start;
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#endif
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#endif /* !defined(CONFIG_CPU_CORTEX_M_HAS_VTOR) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) */
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}
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#if defined(__GNUC__)
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#pragma GCC diagnostic pop
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#endif
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#endif /* CONFIG_CPU_CORTEX_M_HAS_VTOR */
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#if defined(CONFIG_CPU_HAS_FPU)
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static inline void z_arm_floating_point_init(void)
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{
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@ -163,6 +163,10 @@ extern char _image_rodata_size[];
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extern char _vector_start[];
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extern char _vector_end[];
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#ifdef CONFIG_SW_VECTOR_RELAY
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extern char __vector_relay_table[];
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#endif
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#ifdef CONFIG_COVERAGE_GCOV
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extern char __gcov_bss_start[];
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extern char __gcov_bss_end[];
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