2019-04-06 09:08:09 -04:00
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/* SPDX-License-Identifier: Apache-2.0 */
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2018-01-19 14:58:39 -06:00
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/* SoC level DTS fixup file */
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2019-09-19 16:35:52 +02:00
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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2018-11-13 15:15:23 +01:00
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40020000_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020000_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_40020000_LABEL
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#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_40020000_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_40020000_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_40020000_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_40020400_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020400_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_40020400_LABEL
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#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_40020400_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_40020400_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_40020400_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_40020800_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020800_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_40020800_LABEL
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#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_40020800_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_40020800_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_40020800_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_40020C00_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020C00_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_40020C00_LABEL
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#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_40020C00_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_40020C00_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_40020C00_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_40021000_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021000_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_40021000_LABEL
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#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_40021000_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_40021000_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_40021000_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_40021400_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021400_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_40021400_LABEL
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#define DT_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_40021400_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_40021400_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_40021400_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_40021800_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021800_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_40021800_LABEL
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#define DT_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_40021800_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_40021800_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_40021800_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_40021C00_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021C00_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_40021C00_LABEL
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#define DT_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_40021C00_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_40021C00_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_40021C00_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOI_BASE_ADDRESS DT_ST_STM32_GPIO_40022000_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOI_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOI_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOI_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022000_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOI_LABEL DT_ST_STM32_GPIO_40022000_LABEL
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#define DT_GPIO_STM32_GPIOI_SIZE DT_ST_STM32_GPIO_40022000_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOI_CLOCK_BITS DT_ST_STM32_GPIO_40022000_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOI_CLOCK_BUS DT_ST_STM32_GPIO_40022000_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOJ_BASE_ADDRESS DT_ST_STM32_GPIO_40022400_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOJ_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022400_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOJ_LABEL DT_ST_STM32_GPIO_40022400_LABEL
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#define DT_GPIO_STM32_GPIOJ_SIZE DT_ST_STM32_GPIO_40022400_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS DT_ST_STM32_GPIO_40022400_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS DT_ST_STM32_GPIO_40022400_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOK_BASE_ADDRESS DT_ST_STM32_GPIO_40022800_BASE_ADDRESS
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#define DT_GPIO_STM32_GPIOK_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BITS_0
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOK_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BUS_0
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#define DT_GPIO_STM32_GPIOK_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022800_CLOCK_CONTROLLER
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2019-09-19 16:35:52 +02:00
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#define DT_GPIO_STM32_GPIOK_LABEL DT_ST_STM32_GPIO_40022800_LABEL
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#define DT_GPIO_STM32_GPIOK_SIZE DT_ST_STM32_GPIO_40022800_SIZE
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2018-11-13 15:15:23 +01:00
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#define DT_GPIO_STM32_GPIOK_CLOCK_BITS DT_ST_STM32_GPIO_40022800_CLOCK_BITS
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#define DT_GPIO_STM32_GPIOK_CLOCK_BUS DT_ST_STM32_GPIO_40022800_CLOCK_BUS
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2019-09-19 16:35:52 +02:00
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#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS
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#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
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#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
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2019-10-22 09:38:21 -05:00
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#define DT_I2C_1_NAME DT_ST_STM32_I2C_V1_40005400_LABEL
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2019-09-19 16:35:52 +02:00
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#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT
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#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR
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#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
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#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS
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#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS
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#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS
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#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
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#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
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#define DT_I2C_2_NAME DT_ST_STM32_I2C_V1_40005800_LABEL
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2019-09-19 16:35:52 +02:00
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#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT
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#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR
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#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
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#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS
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#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
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#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005C00_BASE_ADDRESS
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#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT_PRIORITY
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#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR_PRIORITY
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2019-10-22 09:38:21 -05:00
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#define DT_I2C_3_NAME DT_ST_STM32_I2C_V1_40005C00_LABEL
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2019-09-19 16:35:52 +02:00
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#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT
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#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR
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#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V1_40005C00_CLOCK_FREQUENCY
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#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BITS
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#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BUS
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#define DT_I2S_1_BASE_ADDRESS DT_ST_STM32_I2S_40013000_BASE_ADDRESS
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#define DT_I2S_1_IRQ_PRI DT_ST_STM32_I2S_40013000_IRQ_0_PRIORITY
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#define DT_I2S_1_NAME DT_ST_STM32_I2S_40013000_LABEL
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#define DT_I2S_1_IRQ DT_ST_STM32_I2S_40013000_IRQ_0
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#define DT_I2S_1_CLOCK_BITS DT_ST_STM32_I2S_40013000_CLOCK_BITS
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#define DT_I2S_1_CLOCK_BUS DT_ST_STM32_I2S_40013000_CLOCK_BUS
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2019-10-24 15:57:17 +08:00
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#define DT_I2S_1_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40013000_TX_DMAS_CONTROLLER
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#define DT_I2S_1_DMA_CHANNEL_TX DT_ST_STM32_I2S_40013000_TX_DMAS_CHANNEL
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#define DT_I2S_1_DMA_SLOT_TX DT_ST_STM32_I2S_40013000_TX_DMAS_SLOT
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#define DT_I2S_1_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40013000_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_1_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40013000_TX_DMAS_FEATURES
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#define DT_I2S_1_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40013000_RX_DMAS_CONTROLLER
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#define DT_I2S_1_DMA_CHANNEL_RX DT_ST_STM32_I2S_40013000_RX_DMAS_CHANNEL
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#define DT_I2S_1_DMA_SLOT_RX DT_ST_STM32_I2S_40013000_RX_DMAS_SLOT
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#define DT_I2S_1_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40013000_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_1_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40013000_RX_DMAS_FEATURES
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2019-09-19 16:35:52 +02:00
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#define DT_I2S_2_BASE_ADDRESS DT_ST_STM32_I2S_40003800_BASE_ADDRESS
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#define DT_I2S_2_IRQ_PRI DT_ST_STM32_I2S_40003800_IRQ_0_PRIORITY
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#define DT_I2S_2_NAME DT_ST_STM32_I2S_40003800_LABEL
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#define DT_I2S_2_IRQ DT_ST_STM32_I2S_40003800_IRQ_0
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#define DT_I2S_2_CLOCK_BITS DT_ST_STM32_I2S_40003800_CLOCK_BITS
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#define DT_I2S_2_CLOCK_BUS DT_ST_STM32_I2S_40003800_CLOCK_BUS
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2019-10-24 15:57:17 +08:00
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#define DT_I2S_2_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40003800_TX_DMAS_CONTROLLER
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#define DT_I2S_2_DMA_CHANNEL_TX DT_ST_STM32_I2S_40003800_TX_DMAS_CHANNEL
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#define DT_I2S_2_DMA_SLOT_TX DT_ST_STM32_I2S_40003800_TX_DMAS_SLOT
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#define DT_I2S_2_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40003800_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_2_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40003800_TX_DMAS_FEATURES
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#define DT_I2S_2_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40003800_RX_DMAS_CONTROLLER
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#define DT_I2S_2_DMA_CHANNEL_RX DT_ST_STM32_I2S_40003800_RX_DMAS_CHANNEL
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#define DT_I2S_2_DMA_SLOT_RX DT_ST_STM32_I2S_40003800_RX_DMAS_SLOT
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#define DT_I2S_2_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40003800_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_2_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40003800_RX_DMAS_FEATURES
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2019-09-19 16:35:52 +02:00
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#define DT_I2S_3_BASE_ADDRESS DT_ST_STM32_I2S_40003C00_BASE_ADDRESS
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#define DT_I2S_3_IRQ_PRI DT_ST_STM32_I2S_40003C00_IRQ_0_PRIORITY
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#define DT_I2S_3_NAME DT_ST_STM32_I2S_40003C00_LABEL
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#define DT_I2S_3_IRQ DT_ST_STM32_I2S_40003C00_IRQ_0
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#define DT_I2S_3_CLOCK_BITS DT_ST_STM32_I2S_40003C00_CLOCK_BITS
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#define DT_I2S_3_CLOCK_BUS DT_ST_STM32_I2S_40003C00_CLOCK_BUS
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2019-10-24 15:57:17 +08:00
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#define DT_I2S_3_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40003C00_TX_DMAS_CONTROLLER
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#define DT_I2S_3_DMA_CHANNEL_TX DT_ST_STM32_I2S_40003C00_TX_DMAS_CHANNEL
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#define DT_I2S_3_DMA_SLOT_TX DT_ST_STM32_I2S_40003C00_TX_DMAS_SLOT
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#define DT_I2S_3_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40003C00_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_3_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40003C00_TX_DMAS_FEATURES
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#define DT_I2S_3_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40003C00_RX_DMAS_CONTROLLER
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#define DT_I2S_3_DMA_CHANNEL_RX DT_ST_STM32_I2S_40003C00_RX_DMAS_CHANNEL
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#define DT_I2S_3_DMA_SLOT_RX DT_ST_STM32_I2S_40003C00_RX_DMAS_SLOT
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#define DT_I2S_3_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40003C00_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_3_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40003C00_RX_DMAS_FEATURES
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2019-09-19 16:35:52 +02:00
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#define DT_I2S_4_BASE_ADDRESS DT_ST_STM32_I2S_40013400_BASE_ADDRESS
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#define DT_I2S_4_IRQ_PRI DT_ST_STM32_I2S_40013400_IRQ_0_PRIORITY
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#define DT_I2S_4_NAME DT_ST_STM32_I2S_40013400_LABEL
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#define DT_I2S_4_IRQ DT_ST_STM32_I2S_40013400_IRQ_0
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#define DT_I2S_4_CLOCK_BITS DT_ST_STM32_I2S_40013400_CLOCK_BITS
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#define DT_I2S_4_CLOCK_BUS DT_ST_STM32_I2S_40013400_CLOCK_BUS
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2019-10-24 15:57:17 +08:00
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#define DT_I2S_4_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40013400_TX_DMAS_CONTROLLER
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#define DT_I2S_4_DMA_CHANNEL_TX DT_ST_STM32_I2S_40013400_TX_DMAS_CHANNEL
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#define DT_I2S_4_DMA_SLOT_TX DT_ST_STM32_I2S_40013400_TX_DMAS_SLOT
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#define DT_I2S_4_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40013400_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_4_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40013400_TX_DMAS_FEATURES
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#define DT_I2S_4_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40013400_RX_DMAS_CONTROLLER
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#define DT_I2S_4_DMA_CHANNEL_RX DT_ST_STM32_I2S_40013400_RX_DMAS_CHANNEL
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#define DT_I2S_4_DMA_SLOT_RX DT_ST_STM32_I2S_40013400_RX_DMAS_SLOT
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#define DT_I2S_4_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40013400_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_4_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40013400_RX_DMAS_FEATURES
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2019-09-19 16:35:52 +02:00
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#define DT_I2S_5_BASE_ADDRESS DT_ST_STM32_I2S_40015000_BASE_ADDRESS
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#define DT_I2S_5_IRQ_PRI DT_ST_STM32_I2S_40015000_IRQ_0_PRIORITY
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#define DT_I2S_5_NAME DT_ST_STM32_I2S_40015000_LABEL
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#define DT_I2S_5_IRQ DT_ST_STM32_I2S_40015000_IRQ_0
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#define DT_I2S_5_CLOCK_BITS DT_ST_STM32_I2S_40015000_CLOCK_BITS
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#define DT_I2S_5_CLOCK_BUS DT_ST_STM32_I2S_40015000_CLOCK_BUS
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2019-10-24 15:57:17 +08:00
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#define DT_I2S_5_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40015000_TX_DMAS_CONTROLLER
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#define DT_I2S_5_DMA_CHANNEL_TX DT_ST_STM32_I2S_40015000_TX_DMAS_CHANNEL
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#define DT_I2S_5_DMA_SLOT_TX DT_ST_STM32_I2S_40015000_TX_DMAS_SLOT
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#define DT_I2S_5_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40015000_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_5_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40015000_TX_DMAS_FEATURES
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#define DT_I2S_5_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40015000_RX_DMAS_CONTROLLER
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#define DT_I2S_5_DMA_CHANNEL_RX DT_ST_STM32_I2S_40015000_RX_DMAS_CHANNEL
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#define DT_I2S_5_DMA_SLOT_RX DT_ST_STM32_I2S_40015000_RX_DMAS_SLOT
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#define DT_I2S_5_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40015000_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_5_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40015000_RX_DMAS_FEATURES
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2019-09-19 16:35:52 +02:00
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#define DT_I2S_6_BASE_ADDRESS DT_ST_STM32_I2S_40015400_BASE_ADDRESS
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#define DT_I2S_6_IRQ_PRI DT_ST_STM32_I2S_40015400_IRQ_0_PRIORITY
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#define DT_I2S_6_NAME DT_ST_STM32_I2S_40015400_LABEL
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#define DT_I2S_6_IRQ DT_ST_STM32_I2S_40015400_IRQ_0
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#define DT_I2S_6_CLOCK_BITS DT_ST_STM32_I2S_40015400_CLOCK_BITS
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#define DT_I2S_6_CLOCK_BUS DT_ST_STM32_I2S_40015400_CLOCK_BUS
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2019-10-24 15:57:17 +08:00
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#define DT_I2S_6_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40015400_TX_DMAS_CONTROLLER
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#define DT_I2S_6_DMA_CHANNEL_TX DT_ST_STM32_I2S_40015400_TX_DMAS_CHANNEL
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#define DT_I2S_6_DMA_SLOT_TX DT_ST_STM32_I2S_40015400_TX_DMAS_SLOT
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#define DT_I2S_6_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40015400_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_6_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40015400_TX_DMAS_FEATURES
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#define DT_I2S_6_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40015400_RX_DMAS_CONTROLLER
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#define DT_I2S_6_DMA_CHANNEL_RX DT_ST_STM32_I2S_40015400_RX_DMAS_CHANNEL
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#define DT_I2S_6_DMA_SLOT_RX DT_ST_STM32_I2S_40015400_RX_DMAS_SLOT
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#define DT_I2S_6_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40015400_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_6_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40015400_RX_DMAS_FEATURES
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2019-09-19 16:35:52 +02:00
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2020-02-27 17:48:19 +01:00
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#define DT_RTC_0_NAME DT_INST_0_ST_STM32_RTC_LABEL
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2018-06-20 19:48:31 +03:00
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2019-07-15 15:47:29 +03:00
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#define DT_WDT_0_NAME DT_INST_0_ST_STM32_WATCHDOG_LABEL
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2020-03-18 21:31:36 +09:00
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL
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2019-01-19 11:30:40 +01:00
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#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
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#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED
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#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL
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#define DT_CAN_1_IRQ_TX DT_ST_STM32_CAN_40006400_IRQ_TX
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#define DT_CAN_1_IRQ_RX0 DT_ST_STM32_CAN_40006400_IRQ_RX0
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#define DT_CAN_1_IRQ_RX1 DT_ST_STM32_CAN_40006400_IRQ_RX1
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#define DT_CAN_1_IRQ_SCE DT_ST_STM32_CAN_40006400_IRQ_SCE
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#define DT_CAN_1_IRQ_PRIORITY DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY
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#define DT_CAN_1_SJW DT_ST_STM32_CAN_40006400_SJW
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#define DT_CAN_1_PROP_SEG DT_ST_STM32_CAN_40006400_PROP_SEG
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#define DT_CAN_1_PHASE_SEG1 DT_ST_STM32_CAN_40006400_PHASE_SEG1
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#define DT_CAN_1_PHASE_SEG2 DT_ST_STM32_CAN_40006400_PHASE_SEG2
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#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
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#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
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2020-01-25 06:59:38 -08:00
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#define DT_CAN_2_BASE_ADDRESS DT_ST_STM32_CAN_40006800_BASE_ADDRESS
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#define DT_CAN_2_BUS_SPEED DT_ST_STM32_CAN_40006800_BUS_SPEED
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#define DT_CAN_2_NAME DT_ST_STM32_CAN_40006800_LABEL
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#define DT_CAN_2_IRQ_TX DT_ST_STM32_CAN_40006800_IRQ_TX
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#define DT_CAN_2_IRQ_RX0 DT_ST_STM32_CAN_40006800_IRQ_RX0
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#define DT_CAN_2_IRQ_RX1 DT_ST_STM32_CAN_40006800_IRQ_RX1
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#define DT_CAN_2_IRQ_SCE DT_ST_STM32_CAN_40006800_IRQ_SCE
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#define DT_CAN_2_IRQ_PRIORITY DT_ST_STM32_CAN_40006800_IRQ_0_PRIORITY
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#define DT_CAN_2_SJW DT_ST_STM32_CAN_40006800_SJW
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#define DT_CAN_2_PROP_SEG DT_ST_STM32_CAN_40006800_PROP_SEG
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#define DT_CAN_2_PHASE_SEG1 DT_ST_STM32_CAN_40006800_PHASE_SEG1
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#define DT_CAN_2_PHASE_SEG2 DT_ST_STM32_CAN_40006800_PHASE_SEG2
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#define DT_CAN_2_CLOCK_BUS DT_ST_STM32_CAN_40006800_CLOCK_BUS
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#define DT_CAN_2_CLOCK_BITS DT_ST_STM32_CAN_40006800_CLOCK_BITS
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2020-03-24 08:23:25 +01:00
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#define DT_FLASH_DEV_NAME DT_INST_0_ST_STM32F4_FLASH_CONTROLLER_LABEL
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2018-01-19 14:58:39 -06:00
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/* End of SoC Level DTS fixup file */
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