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zephyr/boards/arm/mimxrt1050_evk/pinmux.c

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boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <init.h>
#include <fsl_iomuxc.h>
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
#include <fsl_gpio.h>
usdhc/pinmux: configure pinmux of usdhc on mimxrt1050 evk Implementation of pinmux of usdhc depends on board design. Usdhc driver could change pinmux according to SD mode, SoC should provide API for this. Board pinmux should register its pinmux function to SoC. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:23:35 -07:00
#include <soc.h>
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
boards: arm: Conditionalize ethernet pinmuxes on nxp boards Conditionalizes ethernet pinmuxes on CONFIG_NET_L2_ETHERNET for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 09:13:06 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
static gpio_pin_config_t enet_gpio_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0,
.interruptMode = kGPIO_NoIntmode
};
#endif
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
drivers: usdhc: fixup i.MX RT related code after driver relocation Fixup i.MX RT related code after driver relocation. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-02-24 11:07:56 +01:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
usdhc/pinmux: configure pinmux of usdhc on mimxrt1050 evk Implementation of pinmux of usdhc depends on board design. Usdhc driver could change pinmux according to SD mode, SoC should provide API for this. Board pinmux should register its pinmux function to SoC. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:23:35 -07:00
/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
*Speed Field: medium(100MHz)
*Open Drain Enable Field: Open Drain Disabled
*Pull / Keep Enable Field: Pull/Keeper Enabled
*Pull / Keep Select Field: Pull
*Pull Up / Down Config. Field: 47K Ohm Pull Up
*Hyst. Enable Field: Hysteresis Enabled.
*/
static void mimxrt1050_evk_usdhc_pinmux(
zephyr: replace zephyr integer types with C99 types git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-27 11:26:57 -05:00
uint16_t nusdhc, bool init,
uint32_t speed, uint32_t strength)
usdhc/pinmux: configure pinmux of usdhc on mimxrt1050 evk Implementation of pinmux of usdhc depends on board design. Usdhc driver could change pinmux according to SD mode, SoC should provide API for this. Board pinmux should register its pinmux function to SoC. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:23:35 -07:00
{
zephyr: replace zephyr integer types with C99 types git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-27 11:26:57 -05:00
uint32_t cmd_data = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
usdhc/pinmux: configure pinmux of usdhc on mimxrt1050 evk Implementation of pinmux of usdhc depends on board design. Usdhc driver could change pinmux according to SD mode, SoC should provide API for this. Board pinmux should register its pinmux function to SoC. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:23:35 -07:00
IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
zephyr: replace zephyr integer types with C99 types git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-27 11:26:57 -05:00
uint32_t clk = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
usdhc/pinmux: configure pinmux of usdhc on mimxrt1050 evk Implementation of pinmux of usdhc depends on board design. Usdhc driver could change pinmux according to SD mode, SoC should provide API for this. Board pinmux should register its pinmux function to SoC. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:23:35 -07:00
IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
if (nusdhc == 0) {
if (init) {
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,
0U);
IOMUXC_SetPinMux(/*SD_CD*/
IOMUXC_GPIO_B1_12_GPIO2_IO28,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_14_USDHC1_VSELECT,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,
0x10B0u);
IOMUXC_SetPinConfig(/*SD0_CD_SW*/
IOMUXC_GPIO_B1_12_GPIO2_IO28,
0x017089u);
IOMUXC_SetPinConfig(/*SD0_VSELECT*/
IOMUXC_GPIO_B1_14_USDHC1_VSELECT,
0x0170A1u);
}
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
cmd_data);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
clk);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
cmd_data);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
cmd_data);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
cmd_data);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
cmd_data);
}
}
#endif
device: Const-ify all device driver instance pointers Now that device_api attribute is unmodified at runtime, as well as all the other attributes, it is possible to switch all device driver instance to be constant. A coccinelle rule is used for this: @r_const_dev_1 disable optional_qualifier @ @@ -struct device * +const struct device * @r_const_dev_2 disable optional_qualifier @ @@ -struct device * const +const struct device * Fixes #27399 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-04-30 20:33:38 +02:00
static int mimxrt1050_evk_init(const struct device *dev)
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
{
ARG_UNUSED(dev);
CLOCK_EnableClock(kCLOCK_Iomuxc);
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
boards: mimxrt1050_evk: Enable ft5336 touch interrupt Enables the ft5336 touch controller interrupt on the mimxrt1050_evk board. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-04-28 20:20:22 -05:00
#if DT_NODE_HAS_PROP(DT_INST(0, focaltech_ft5336), int_gpios)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_GPIO1_IO11,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
boards: arm: Fix conditionalized pinmuxes for shared pin A change was put in to conditionalize pinmuxes based on Ethernet configuration but for the IMXRT1050/60/64-EVK boards the USER_LED and ENET_RST share the same GPIO. Samples like blinky would not work on these boards. The change is to not conditionalize the shared pin. fixes: #27473 Signed-off-by: David Leach <david.leach@nxp.com>
2020-08-12 14:37:21 -05:00
#if !CONFIG_NET_L2_ETHERNET
/* Shared GPIO between USER_LED and ENET_RST */
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
/* SW0 */
IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
#endif
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
boards: arm: Conditionalize serial pinmuxes on nxp boards Conditionalizes serial pinmuxes on CONFIG_SERIAL for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 08:32:04 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
/* LPUART1 TX/RX */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
boards: arm: Conditionalize serial pinmuxes on nxp boards Conditionalizes serial pinmuxes on CONFIG_SERIAL for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 08:32:04 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart3), okay) && CONFIG_SERIAL
boards: mimxrt1050_evk: Enable lpuart3 for bluetooth hci Enables instance 3 of the lpuart driver, adds dts fixups, and configures pinmuxes to use bluetooth hci on the mimxrt1050_evk board. Updates board documentation accordingly. Tested with samples/bluetooth/peripheral_hr, with frdm_kw41z attached as an arduino shield running the nxp hci controller application. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-24 11:26:59 -05:00
/* LPUART3 TX/RX */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
boards: arm: Conditionalize i2c pinmuxes on nxp boards Conditionalizes i2c pinmuxes on CONFIG_I2C for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 08:52:08 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) && CONFIG_I2C
boards: mimxrt1050_evk: Enable mcux lpi2c driver and pins Enables the mcux lpi2c shim driver and pin muxes on the mimxrt1050_evk board. Updates the board documentation and yaml supported list accordingly. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-17 07:07:24 -06:00
/* LPI2C1 SCL, SDA */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
boards: mimxrt1050_evk: Added support for LPSPI1 peripheral RT1050 has multiple LPSPI peripherals. The simplest to access is LPSPI1, which can be connected by bridging solder jumpers on the board. Enable this SPI peripheral, and set it as default for SPI tests. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-10-08 09:55:38 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) && CONFIG_SPI
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
#error "SPI and SDMMC pins conflict on this board." \
"Please disable one via KConfig or device tree"
#else
/* LPSPI1 SCK, SDO, SDI, PCS0 */
/* Expose these pins by connecting R278, R279, R280, and R281 on evk board */
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
#endif
boards: arm: Conditionalize spi pinmuxes on nxp boards Conditionalizes spi pinmuxes on CONFIG_SPI for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 08:47:13 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi3), okay) && CONFIG_SPI
mimxrt1050_evk: Configure an lpspi instance and pins Enables an instance of the lpspi peripheral, configures the pinmuxes, and updates the board documentation accordingly. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-14 16:23:27 -05:00
/* LPSPI3 SCK, SDO, SDI, PCS0 */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
boards: arm: Conditionalize ethernet pinmuxes on nxp boards Conditionalizes ethernet pinmuxes on CONFIG_NET_L2_ETHERNET for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 09:13:06 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U);
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
boards: arm: Fix conditionalized pinmuxes for shared pin A change was put in to conditionalize pinmuxes based on Ethernet configuration but for the IMXRT1050/60/64-EVK boards the USER_LED and ENET_RST share the same GPIO. Samples like blinky would not work on these boards. The change is to not conditionalize the shared pin. fixes: #27473 Signed-off-by: David Leach <david.leach@nxp.com>
2020-08-12 14:37:21 -05:00
/* Shared GPIO between USER_LED and ENET_RST */
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0xB0A9u);
boards: arm: Fix conditionalized pinmuxes for shared pin A change was put in to conditionalize pinmuxes based on Ethernet configuration but for the IMXRT1050/60/64-EVK boards the USER_LED and ENET_RST share the same GPIO. Samples like blinky would not work on these boards. The change is to not conditionalize the shared pin. fixes: #27473 Signed-off-by: David Leach <david.leach@nxp.com>
2020-08-12 14:37:21 -05:00
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0xB0A9u);
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0x31);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB829);
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
/* Intialize ENET_INT GPIO */
GPIO_PinInit(GPIO1, 9, &enet_gpio_config);
GPIO_PinInit(GPIO1, 10, &enet_gpio_config);
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 10, 1);
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
GPIO_WritePinOutput(GPIO1, 9, 0);
#endif
boards: arm: Conditionalize display pinmuxes on nxp boards Conditionalizes display pinmuxes on CONFIG_DISPLAY for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 09:27:18 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lcdif), okay) && CONFIG_DISPLAY
boards: mimxrt1050_evk: Enable mcux elcdif driver and pins Enables the mcux elcdif shim driver and pin muxes on the mimxrt1050_evk board. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:51:51 -06:00
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0u);
/* LCD Reset */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0x10B0u);
/* LCD Backlight */
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0u);
gpio_pin_config_t config = {
kGPIO_DigitalOutput, 0,
};
config.outputLogic = 1;
GPIO_PinInit(GPIO2, 31, &config);
#endif
boards: arm: mimxrt1050_evk: added support for hyperflash This is all the settings for the hyperflash driver in the dts. Signed-off-by: Nicolai Glud <nicolai.glud@prevas.dk>
2021-09-20 13:03:57 +02:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) && CONFIG_FLASH_MCUX_FLEXSPI_HYPERFLASH
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0x0130F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0x10F1U);
#endif
drivers: usdhc: fixup i.MX RT related code after driver relocation Fixup i.MX RT related code after driver relocation. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-02-24 11:07:56 +01:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
usdhc/pinmux: configure pinmux of usdhc on mimxrt1050 evk Implementation of pinmux of usdhc depends on board design. Usdhc driver could change pinmux according to SD mode, SoC should provide API for this. Board pinmux should register its pinmux function to SoC. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:23:35 -07:00
mimxrt1050_evk_usdhc_pinmux(0, true, 2, 1);
imxrt_usdhc_pinmux_cb_register(mimxrt1050_evk_usdhc_pinmux);
#endif
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
return 0;
}
boards: arm: Conditionalize ethernet pinmuxes on nxp boards Conditionalizes ethernet pinmuxes on CONFIG_NET_L2_ETHERNET for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 09:13:06 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
device: Const-ify all device driver instance pointers Now that device_api attribute is unmodified at runtime, as well as all the other attributes, it is possible to switch all device driver instance to be constant. A coccinelle rule is used for this: @r_const_dev_1 disable optional_qualifier @ @@ -struct device * +const struct device * @r_const_dev_2 disable optional_qualifier @ @@ -struct device * const +const struct device * Fixes #27399 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-04-30 20:33:38 +02:00
static int mimxrt1050_evk_phy_reset(const struct device *dev)
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
{
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
/* RESET PHY chip. */
all: Update unsigend 'U' suffix due to multiplication As the multiplication rule is updated, new unsigned suffixes are added in the code. Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-28 14:57:54 -06:00
k_busy_wait(USEC_PER_MSEC * 10U);
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
GPIO_WritePinOutput(GPIO1, 9, 1);
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
return 0;
}
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
#endif
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0);
boards: arm: Conditionalize ethernet pinmuxes on nxp boards Conditionalizes ethernet pinmuxes on CONFIG_NET_L2_ETHERNET for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-21 09:13:06 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
boards: arm: Reset Ethernet PHY after system timer on mimxrt1xxx_evk's Moves the Ethernet PHY reset routine on mimxrt1xxx_evk boards to execute in the POST_KERNEL initialization level rather than the PRE_KERNEL_2 level because it relies on a kernel service, k_busy_wait(). Leverages the existing CONFIG_PHY_INIT_PRIORITY to allow users to configure when within the POST_KERNEL level this routine occurs, which by default is set correctly to the following order: Init Function Init Level Priority -------------------------------------------------------------------------------------- sys_clock_driver_init PRE_KERNEL_2 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY=0 mcux_igpio_##n##_init POST_KERNEL CONFIG_KERNEL_INIT_PRIORITY_DEFAULT=40 mimxrt1064_evk_phy_reset POST_KERNEL CONFIG_PHY_INIT_PRIORITY=70 eth_init POST_KERNEL CONFIG_ETH_INIT_PRIORITY=80 net_init POST_KERNEL CONFIG_NET_INIT_PRIO=90 This fixes an issue that was introduced in commit f0b3146ff5538e5381318a309fec292d3fbb1f3f, which caused the system timer to be initialized after the Ethernet PHY reset. As a result, the k_busy_wait() never returned and the kernel never finished booting. The serial driver never initialized and there was no output on the console, not even a boot banner. Tested on the mimxrt1064_evk board with samples/net/dhcpv4_client. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-09-10 17:12:51 -05:00
SYS_INIT(mimxrt1050_evk_phy_reset, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY);
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
#endif
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