boards: arm: Add NXP mimxrt1050_evk
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
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/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <fsl_iomuxc.h>
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2018-11-15 18:28:47 +02:00
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#include <fsl_gpio.h>
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2019-07-03 21:23:35 -07:00
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#include <soc.h>
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2018-11-15 18:28:47 +02:00
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2020-04-14 10:25:31 -05:00
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#if DT_HAS_NODE(DT_NODELABEL(enet))
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2018-11-15 18:28:47 +02:00
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static gpio_pin_config_t enet_gpio_config = {
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.direction = kGPIO_DigitalOutput,
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.outputLogic = 0,
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.interruptMode = kGPIO_NoIntmode
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};
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#endif
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boards: arm: Add NXP mimxrt1050_evk
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
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2020-04-14 10:25:31 -05:00
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#if DT_HAS_NODE(DT_NODELABEL(usdhc1)) && CONFIG_DISK_ACCESS_USDHC1
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2019-07-03 21:23:35 -07:00
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/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
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*Speed Field: medium(100MHz)
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*Open Drain Enable Field: Open Drain Disabled
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*Pull / Keep Enable Field: Pull/Keeper Enabled
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*Pull / Keep Select Field: Pull
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*Pull Up / Down Config. Field: 47K Ohm Pull Up
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*Hyst. Enable Field: Hysteresis Enabled.
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*/
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static void mimxrt1050_evk_usdhc_pinmux(
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u16_t nusdhc, bool init,
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u32_t speed, u32_t strength)
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{
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u32_t cmd_data = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
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IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
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u32_t clk = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
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IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
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if (nusdhc == 0) {
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if (init) {
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,
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0U);
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IOMUXC_SetPinMux(/*SD_CD*/
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IOMUXC_GPIO_B1_12_GPIO2_IO28,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_14_USDHC1_VSELECT,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,
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0x10B0u);
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IOMUXC_SetPinConfig(/*SD0_CD_SW*/
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IOMUXC_GPIO_B1_12_GPIO2_IO28,
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0x017089u);
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IOMUXC_SetPinConfig(/*SD0_VSELECT*/
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IOMUXC_GPIO_B1_14_USDHC1_VSELECT,
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0x0170A1u);
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}
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
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cmd_data);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
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clk);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
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cmd_data);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
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cmd_data);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
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cmd_data);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
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cmd_data);
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}
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}
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#endif
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|
boards: arm: Add NXP mimxrt1050_evk
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
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static int mimxrt1050_evk_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
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2020-04-14 10:25:31 -05:00
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#if !DT_HAS_NODE(DT_NODELABEL(enet))
|
boards: arm: Add NXP mimxrt1050_evk
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
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/* LED */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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/* SW0 */
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IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
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2018-12-14 16:58:21 +02:00
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#endif
|
boards: arm: Add NXP mimxrt1050_evk
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
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2020-04-14 10:25:31 -05:00
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#if DT_HAS_NODE(DT_NODELABEL(lpuart1))
|
boards: arm: Add NXP mimxrt1050_evk
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
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/* LPUART1 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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2020-04-14 10:25:31 -05:00
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#if DT_HAS_NODE(DT_NODELABEL(lpuart3))
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2018-09-24 11:26:59 -05:00
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/* LPUART3 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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|
2020-04-14 10:25:31 -05:00
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#if DT_HAS_NODE(DT_NODELABEL(lpi2c1))
|
2019-01-17 07:07:24 -06:00
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/* LPI2C1 SCL, SDA */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
|
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,
|
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
|
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
|
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
|
|
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
|
|
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
|
|
|
|
|
#endif
|
|
|
|
|
|
2020-04-14 10:25:31 -05:00
|
|
|
#if DT_HAS_NODE(DT_NODELABEL(lpspi3))
|
2018-09-14 16:23:27 -05:00
|
|
|
/* LPSPI3 SCK, SDO, SDI, PCS0 */
|
|
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK, 0);
|
|
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0, 0);
|
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK,
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
|
|
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|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
|
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|
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|
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO,
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
|
|
|
|
|
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI,
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
|
|
|
|
|
|
|
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|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0,
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
|
|
|
|
|
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
|
|
|
|
|
#endif
|
|
|
|
|
|
2020-04-14 10:25:31 -05:00
|
|
|
#if DT_HAS_NODE(DT_NODELABEL(enet))
|
2018-12-14 16:58:21 +02:00
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U);
|
2018-11-15 18:28:47 +02:00
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
|
|
|
|
|
|
2018-12-14 16:58:21 +02:00
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0xB0A9u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0xB0A9u);
|
2018-11-15 18:28:47 +02:00
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB0E9);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB0E9);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB0E9);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB0E9);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB0E9);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB0E9);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0x31);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB0E9);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB0E9);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB829);
|
|
|
|
|
|
|
|
|
|
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
|
|
|
|
|
|
|
|
|
|
/* Intialize ENET_INT GPIO */
|
|
|
|
|
GPIO_PinInit(GPIO1, 9, &enet_gpio_config);
|
|
|
|
|
GPIO_PinInit(GPIO1, 10, &enet_gpio_config);
|
|
|
|
|
|
|
|
|
|
/* pull up the ENET_INT before RESET. */
|
|
|
|
|
GPIO_WritePinOutput(GPIO1, 10, 1);
|
2019-01-31 13:00:56 +02:00
|
|
|
GPIO_WritePinOutput(GPIO1, 9, 0);
|
|
|
|
|
#endif
|
|
|
|
|
|
2020-04-14 10:25:31 -05:00
|
|
|
#if DT_HAS_NODE(DT_NODELABEL(lcdif))
|
2019-01-02 13:51:51 -06:00
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0);
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0);
|
|
|
|
|
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0u);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0u);
|
|
|
|
|
|
|
|
|
|
/* LCD Reset */
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0x10B0u);
|
|
|
|
|
|
|
|
|
|
/* LCD Backlight */
|
|
|
|
|
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0);
|
|
|
|
|
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0u);
|
|
|
|
|
|
|
|
|
|
gpio_pin_config_t config = {
|
|
|
|
|
kGPIO_DigitalOutput, 0,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
config.outputLogic = 1;
|
|
|
|
|
GPIO_PinInit(GPIO2, 31, &config);
|
|
|
|
|
#endif
|
|
|
|
|
|
2020-04-14 10:25:31 -05:00
|
|
|
#if DT_HAS_NODE(DT_NODELABEL(usdhc1)) && CONFIG_DISK_ACCESS_USDHC1
|
2019-07-03 21:23:35 -07:00
|
|
|
mimxrt1050_evk_usdhc_pinmux(0, true, 2, 1);
|
|
|
|
|
imxrt_usdhc_pinmux_cb_register(mimxrt1050_evk_usdhc_pinmux);
|
|
|
|
|
#endif
|
|
|
|
|
|
2019-01-31 13:00:56 +02:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-04-14 10:25:31 -05:00
|
|
|
#if DT_HAS_NODE(DT_NODELABEL(enet))
|
2019-01-31 13:00:56 +02:00
|
|
|
static int mimxrt1050_evk_phy_reset(struct device *dev)
|
|
|
|
|
{
|
2018-11-15 18:28:47 +02:00
|
|
|
/* RESET PHY chip. */
|
2019-03-28 14:57:54 -06:00
|
|
|
k_busy_wait(USEC_PER_MSEC * 10U);
|
2018-11-15 18:28:47 +02:00
|
|
|
GPIO_WritePinOutput(GPIO1, 9, 1);
|
|
|
|
|
|
boards: arm: Add NXP mimxrt1050_evk
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
|
|
|
return 0;
|
|
|
|
|
}
|
2019-01-31 13:00:56 +02:00
|
|
|
#endif
|
boards: arm: Add NXP mimxrt1050_evk
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
|
|
|
|
2018-12-14 16:58:21 +02:00
|
|
|
SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0);
|
2020-04-14 10:25:31 -05:00
|
|
|
#if DT_HAS_NODE(DT_NODELABEL(enet))
|
2019-01-31 13:00:56 +02:00
|
|
|
SYS_INIT(mimxrt1050_evk_phy_reset, PRE_KERNEL_2, 0);
|
|
|
|
|
#endif
|
