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zephyr/boards/arm/mimxrt1050_evk/pinmux.c

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boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <init.h>
#include <fsl_iomuxc.h>
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
#include <fsl_gpio.h>
#ifdef CONFIG_ETH_MCUX_0
static gpio_pin_config_t enet_gpio_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0,
.interruptMode = kGPIO_NoIntmode
};
#endif
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
static int mimxrt1050_evk_init(struct device *dev)
{
ARG_UNUSED(dev);
CLOCK_EnableClock(kCLOCK_Iomuxc);
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
#ifndef CONFIG_ETH_MCUX_0
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
/* LED */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
/* SW0 */
IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
#endif
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
#ifdef CONFIG_UART_MCUX_LPUART_1
/* LPUART1 TX/RX */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
boards: mimxrt1050_evk: Enable lpuart3 for bluetooth hci Enables instance 3 of the lpuart driver, adds dts fixups, and configures pinmuxes to use bluetooth hci on the mimxrt1050_evk board. Updates board documentation accordingly. Tested with samples/bluetooth/peripheral_hr, with frdm_kw41z attached as an arduino shield running the nxp hci controller application. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-24 11:26:59 -05:00
#ifdef CONFIG_UART_MCUX_LPUART_3
/* LPUART3 TX/RX */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
boards: mimxrt1050_evk: Enable mcux lpi2c driver and pins Enables the mcux lpi2c shim driver and pin muxes on the mimxrt1050_evk board. Updates the board documentation and yaml supported list accordingly. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-17 07:07:24 -06:00
#ifdef CONFIG_I2C_1
/* LPI2C1 SCL, SDA */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,
IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
mimxrt1050_evk: Configure an lpspi instance and pins Enables an instance of the lpspi peripheral, configures the pinmuxes, and updates the board documentation accordingly. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-14 16:23:27 -05:00
#ifdef CONFIG_SPI_3
/* LPSPI3 SCK, SDO, SDI, PCS0 */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
#ifdef CONFIG_ETH_MCUX_0
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U);
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0xB0A9u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0xB0A9u);
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0x31);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB829);
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
/* Intialize ENET_INT GPIO */
GPIO_PinInit(GPIO1, 9, &enet_gpio_config);
GPIO_PinInit(GPIO1, 10, &enet_gpio_config);
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 10, 1);
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
GPIO_WritePinOutput(GPIO1, 9, 0);
#endif
boards: mimxrt1050_evk: Enable mcux elcdif driver and pins Enables the mcux elcdif shim driver and pin muxes on the mimxrt1050_evk board. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:51:51 -06:00
#ifdef CONFIG_DISPLAY_MCUX_ELCDIF
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0u);
/* LCD Reset */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0x10B0u);
/* LCD Backlight */
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0u);
gpio_pin_config_t config = {
kGPIO_DigitalOutput, 0,
};
config.outputLogic = 1;
GPIO_PinInit(GPIO2, 31, &config);
#endif
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
return 0;
}
#ifdef CONFIG_ETH_MCUX_0
static int mimxrt1050_evk_phy_reset(struct device *dev)
{
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
/* RESET PHY chip. */
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
k_busy_wait(10*USEC_PER_MSEC);
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
GPIO_WritePinOutput(GPIO1, 9, 1);
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
return 0;
}
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
#endif
boards: arm: Add NXP mimxrt1050_evk Adds support for the NXP MIMXRT1050-EVK board, an entry-level development board for the new mimxrt1052 Cortex-M7 SoC. Adds pinmuxing, dts, documentation, and jlink debug support for the new board. Note that pinmuxing uses the mcux pinmux driver directly rather than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated pinmuxing that may require changing the Zephyr pinmux interface to support, so for now let's use the mcux driver directly. We are also not yet configuring the external flash, therefore a debugger is required to load code to the internal sram. The on-board OpenSDA circuit with jlink firmware is sufficient, and the 'make debug' build target is supported. Samples tested include: hello_world, philosophers, synchronization, basic/blinky, and basic/button. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:46:04 -05:00
mimix1050rt: ethernet initialization corrected Fixes board PHY initialization. ENET_RST and ENET_INT pins are also used as USER_LED/JTAG_TDI and INT1_COMBO/JTAG_TDO. Initialization needs to set these pins to power and interrupt for the PHY Transciver. PHY reset works without busy waiting. Moved pin initialization back to PRE_KERNEL_1 to fix UART bug and busy wait not required. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-12-14 16:58:21 +02:00
SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0);
mimxrt1050_evk: eth_mcux: driver fixup Boot PHY initialization timeout, caching mechanism fixes and networking buffer descriptors moved to no cache section. Enabled cache management in networking driver and manual barriers. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:00:56 +02:00
#ifdef CONFIG_ETH_MCUX_0
SYS_INIT(mimxrt1050_evk_phy_reset, PRE_KERNEL_2, 0);
#endif
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