2016-11-25 17:21:26 +01:00
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/*
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* Copyright (c) 2016 Linaro Limited.
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2020-04-21 21:50:03 +02:00
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* Copyright (c) 2020 Teslabs Engineering S.L.
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2023-06-01 08:29:59 +02:00
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* Copyright (c) 2023 Nobleo Technology
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2016-11-25 17:21:26 +01:00
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*
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2017-01-19 02:01:01 +01:00
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* SPDX-License-Identifier: Apache-2.0
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2016-11-25 17:21:26 +01:00
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*/
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2020-03-24 20:28:48 +01:00
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#define DT_DRV_COMPAT st_stm32_pwm
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2016-11-25 17:21:26 +01:00
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#include <errno.h>
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2018-10-31 18:44:45 +01:00
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#include <soc.h>
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2020-11-20 15:52:57 +01:00
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_tim.h>
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2022-05-06 10:25:46 +02:00
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/pinctrl.h>
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2023-06-23 08:24:07 +02:00
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#include <zephyr/drivers/reset.h>
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2022-05-06 10:25:46 +02:00
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/init.h>
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2016-11-25 17:21:26 +01:00
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2022-05-06 10:25:46 +02:00
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
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2016-11-25 17:21:26 +01:00
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2022-05-06 10:25:46 +02:00
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#include <zephyr/logging/log.h>
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2022-10-17 10:24:11 +02:00
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#include <zephyr/irq.h>
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2022-06-17 16:15:11 +02:00
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2020-04-21 21:50:03 +02:00
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LOG_MODULE_REGISTER(pwm_stm32, CONFIG_PWM_LOG_LEVEL);
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2020-12-15 15:19:39 +01:00
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/* L0 series MCUs only have 16-bit timers and don't have below macro defined */
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#ifndef IS_TIM_32B_COUNTER_INSTANCE
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#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
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#endif
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2021-10-26 15:08:30 +02:00
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#ifdef CONFIG_PWM_CAPTURE
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2023-06-01 08:29:59 +02:00
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/**
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* @brief Capture state when in 4-channel support mode
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*/
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enum capture_state {
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CAPTURE_STATE_IDLE = 0,
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CAPTURE_STATE_WAIT_FOR_UPDATE_EVENT = 1,
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CAPTURE_STATE_WAIT_FOR_PULSE_START = 2,
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CAPTURE_STATE_WAIT_FOR_PERIOD_END = 3
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};
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/** Return the complimentary channel number
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* that is used to capture the end of the pulse.
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*/
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static const uint32_t complimentary_channel[] = {0, 2, 1, 4, 3};
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2021-10-26 15:08:30 +02:00
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struct pwm_stm32_capture_data {
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pwm_capture_callback_handler_t callback;
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void *user_data;
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uint32_t period;
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uint32_t pulse;
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uint32_t overflows;
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uint8_t skip_irq;
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bool capture_period;
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bool capture_pulse;
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bool continuous;
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2023-06-01 08:29:59 +02:00
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uint8_t channel;
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/* only used when four_channel_capture_support */
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enum capture_state state;
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2021-10-26 15:08:30 +02:00
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};
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2022-01-25 10:49:28 +01:00
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2023-06-01 08:29:59 +02:00
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/* When PWM capture is done by resetting the counter with UIF then the
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* first capture is always nonsense, second is nonsense when polarity changed
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* This is not the case when using four-channel-support.
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*/
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2022-01-25 10:49:28 +01:00
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#define SKIPPED_PWM_CAPTURES 2u
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2021-10-26 15:08:30 +02:00
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#endif /*CONFIG_PWM_CAPTURE*/
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2020-04-21 21:50:03 +02:00
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/** PWM data. */
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struct pwm_stm32_data {
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/** Timer clock (Hz). */
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uint32_t tim_clk;
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2023-06-23 08:24:07 +02:00
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/* Reset controller device configuration */
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const struct reset_dt_spec reset;
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2021-10-26 15:08:30 +02:00
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#ifdef CONFIG_PWM_CAPTURE
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struct pwm_stm32_capture_data capture;
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#endif /* CONFIG_PWM_CAPTURE */
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2020-04-21 21:50:03 +02:00
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};
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/** PWM configuration. */
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struct pwm_stm32_config {
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TIM_TypeDef *timer;
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uint32_t prescaler;
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2022-04-11 11:50:22 +02:00
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uint32_t countermode;
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2020-04-21 21:50:03 +02:00
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struct stm32_pclken pclken;
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2021-11-08 11:42:44 +01:00
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const struct pinctrl_dev_config *pcfg;
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2021-10-26 15:08:30 +02:00
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#ifdef CONFIG_PWM_CAPTURE
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void (*irq_config_func)(const struct device *dev);
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2023-06-01 08:29:59 +02:00
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const bool four_channel_capture_support;
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2021-10-26 15:08:30 +02:00
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#endif /* CONFIG_PWM_CAPTURE */
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2020-04-21 21:50:03 +02:00
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};
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2019-11-13 09:02:51 +01:00
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2022-01-25 10:49:28 +01:00
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/** Maximum number of timer channels : some stm32 soc have 6 else only 4 */
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#if defined(LL_TIM_CHANNEL_CH6)
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2021-02-18 10:08:57 +01:00
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#define TIMER_HAS_6CH 1
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2020-04-21 21:50:03 +02:00
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#define TIMER_MAX_CH 6u
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#else
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2022-01-25 10:49:28 +01:00
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#define TIMER_HAS_6CH 0
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2020-04-21 21:50:03 +02:00
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#define TIMER_MAX_CH 4u
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#endif
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2016-11-25 17:21:26 +01:00
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2020-04-21 21:50:03 +02:00
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/** Channel to LL mapping. */
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static const uint32_t ch2ll[TIMER_MAX_CH] = {
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LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2,
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LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4,
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#if TIMER_HAS_6CH
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LL_TIM_CHANNEL_CH5, LL_TIM_CHANNEL_CH6
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#endif
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};
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2016-11-25 17:21:26 +01:00
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2022-01-25 10:49:28 +01:00
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/** Some stm32 mcus have complementary channels : 3 or 4 */
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static const uint32_t ch2ll_n[] = {
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#if defined(LL_TIM_CHANNEL_CH1N)
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LL_TIM_CHANNEL_CH1N,
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LL_TIM_CHANNEL_CH2N,
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LL_TIM_CHANNEL_CH3N,
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#if defined(LL_TIM_CHANNEL_CH4N)
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/** stm32g4x and stm32u5x have 4 complementary channels */
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LL_TIM_CHANNEL_CH4N,
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#endif /* LL_TIM_CHANNEL_CH4N */
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#endif /* LL_TIM_CHANNEL_CH1N */
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};
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/** Maximum number of complemented timer channels is ARRAY_SIZE(ch2ll_n)*/
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2020-04-21 21:50:03 +02:00
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/** Channel to compare set function mapping. */
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static void (*const set_timer_compare[TIMER_MAX_CH])(TIM_TypeDef *,
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uint32_t) = {
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LL_TIM_OC_SetCompareCH1, LL_TIM_OC_SetCompareCH2,
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LL_TIM_OC_SetCompareCH3, LL_TIM_OC_SetCompareCH4,
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#if TIMER_HAS_6CH
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LL_TIM_OC_SetCompareCH5, LL_TIM_OC_SetCompareCH6
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#endif
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};
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2023-06-01 08:29:59 +02:00
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/** Channel to capture get function mapping. */
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2024-04-19 10:07:59 +02:00
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#if !defined(CONFIG_SOC_SERIES_STM32MP1X)
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2023-06-01 08:29:59 +02:00
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static uint32_t __maybe_unused (*const get_channel_capture[])(const TIM_TypeDef *) = {
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#else
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static uint32_t __maybe_unused (*const get_channel_capture[])(TIM_TypeDef *) = {
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#endif
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LL_TIM_IC_GetCaptureCH1, LL_TIM_IC_GetCaptureCH2,
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LL_TIM_IC_GetCaptureCH3, LL_TIM_IC_GetCaptureCH4
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};
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/** Channel to enable capture interrupt mapping. */
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static void __maybe_unused (*const enable_capture_interrupt[])(TIM_TypeDef *) = {
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LL_TIM_EnableIT_CC1, LL_TIM_EnableIT_CC2,
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LL_TIM_EnableIT_CC3, LL_TIM_EnableIT_CC4
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};
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/** Channel to disable capture interrupt mapping. */
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static void __maybe_unused (*const disable_capture_interrupt[])(TIM_TypeDef *) = {
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LL_TIM_DisableIT_CC1, LL_TIM_DisableIT_CC2,
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LL_TIM_DisableIT_CC3, LL_TIM_DisableIT_CC4
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};
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/** Channel to is capture active flag mapping. */
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2024-04-19 10:07:59 +02:00
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#if !defined(CONFIG_SOC_SERIES_STM32MP1X)
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2023-06-01 08:29:59 +02:00
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static uint32_t __maybe_unused (*const is_capture_active[])(const TIM_TypeDef *) = {
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#else
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static uint32_t __maybe_unused (*const is_capture_active[])(TIM_TypeDef *) = {
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#endif
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LL_TIM_IsActiveFlag_CC1, LL_TIM_IsActiveFlag_CC2,
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LL_TIM_IsActiveFlag_CC3, LL_TIM_IsActiveFlag_CC4
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};
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/** Channel to clearing capture flag mapping. */
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static void __maybe_unused (*const clear_capture_interrupt[])(TIM_TypeDef *) = {
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LL_TIM_ClearFlag_CC1, LL_TIM_ClearFlag_CC2,
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LL_TIM_ClearFlag_CC3, LL_TIM_ClearFlag_CC4
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};
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2020-04-23 16:10:12 +02:00
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/**
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* Obtain LL polarity from PWM flags.
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*
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* @param flags PWM flags.
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*
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* @return LL polarity.
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*/
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static uint32_t get_polarity(pwm_flags_t flags)
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{
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2020-07-06 19:57:34 +02:00
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if ((flags & PWM_POLARITY_MASK) == PWM_POLARITY_NORMAL) {
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2020-04-23 16:10:12 +02:00
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return LL_TIM_OCPOLARITY_HIGH;
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}
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return LL_TIM_OCPOLARITY_LOW;
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}
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2022-04-11 11:50:22 +02:00
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/**
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* @brief Check if LL counter mode is center-aligned.
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*
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* @param ll_countermode LL counter mode.
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*
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* @return `true` when center-aligned, otherwise `false`.
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*/
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static inline bool is_center_aligned(const uint32_t ll_countermode)
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{
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return ((ll_countermode == LL_TIM_COUNTERMODE_CENTER_DOWN) ||
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(ll_countermode == LL_TIM_COUNTERMODE_CENTER_UP) ||
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(ll_countermode == LL_TIM_COUNTERMODE_CENTER_UP_DOWN));
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}
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2020-04-21 21:50:03 +02:00
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/**
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* Obtain timer clock speed.
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*
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* @param pclken Timer clock control subsystem.
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* @param tim_clk Where computed timer clock will be stored.
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*
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* @return 0 on success, error code otherwise.
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*/
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static int get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk)
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{
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int r;
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2020-04-30 20:33:38 +02:00
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const struct device *clk;
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2020-04-21 21:50:03 +02:00
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uint32_t bus_clk, apb_psc;
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2021-02-11 18:49:24 +01:00
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clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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2020-04-21 21:50:03 +02:00
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2023-03-28 08:24:07 +02:00
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r = clock_control_get_rate(clk, (clock_control_subsys_t)pclken,
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2020-04-21 21:50:03 +02:00
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&bus_clk);
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if (r < 0) {
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return r;
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}
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2017-01-24 11:09:06 +01:00
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2020-03-07 17:58:35 +01:00
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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if (pclken->bus == STM32_CLOCK_BUS_APB1) {
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2021-05-05 12:13:48 +02:00
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apb_psc = STM32_D2PPRE1;
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2020-03-07 17:58:35 +01:00
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} else {
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2021-05-05 12:13:48 +02:00
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apb_psc = STM32_D2PPRE2;
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2020-03-07 17:58:35 +01:00
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}
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2020-10-16 20:07:27 +02:00
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#else
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if (pclken->bus == STM32_CLOCK_BUS_APB1) {
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2023-07-04 16:24:53 +02:00
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#if defined(CONFIG_SOC_SERIES_STM32MP1X)
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apb_psc = (uint32_t)(READ_BIT(RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV));
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#else
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2021-03-31 15:46:10 +02:00
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apb_psc = STM32_APB1_PRESCALER;
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2023-07-04 16:24:53 +02:00
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#endif
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2020-10-16 20:07:27 +02:00
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}
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2023-03-19 11:27:32 +01:00
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#if !defined(CONFIG_SOC_SERIES_STM32C0X) && !defined(CONFIG_SOC_SERIES_STM32F0X) && \
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!defined(CONFIG_SOC_SERIES_STM32G0X)
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2020-10-16 20:07:27 +02:00
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else {
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2023-07-04 16:24:53 +02:00
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#if defined(CONFIG_SOC_SERIES_STM32MP1X)
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apb_psc = (uint32_t)(READ_BIT(RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV));
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#else
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2021-03-31 15:46:10 +02:00
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apb_psc = STM32_APB2_PRESCALER;
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2023-07-04 16:24:53 +02:00
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#endif
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2020-10-16 20:07:27 +02:00
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}
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#endif
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#endif
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2020-03-07 17:58:35 +01:00
|
|
|
|
|
2020-10-16 20:07:27 +02:00
|
|
|
|
#if defined(RCC_DCKCFGR_TIMPRE) || defined(RCC_DCKCFGR1_TIMPRE) || \
|
|
|
|
|
defined(RCC_CFGR_TIMPRE)
|
2020-03-07 17:58:35 +01:00
|
|
|
|
/*
|
2020-10-16 20:07:27 +02:00
|
|
|
|
* There are certain series (some F4, F7 and H7) that have the TIMPRE
|
|
|
|
|
* bit to control the clock frequency of all the timers connected to
|
|
|
|
|
* APB1 and APB2 domains.
|
2020-03-07 17:58:35 +01:00
|
|
|
|
*
|
2020-10-16 20:07:27 +02:00
|
|
|
|
* Up to a certain threshold value of APB{1,2} prescaler, timer clock
|
|
|
|
|
* equals to HCLK. This threshold value depends on TIMPRE setting
|
|
|
|
|
* (2 if TIMPRE=0, 4 if TIMPRE=1). Above threshold, timer clock is set
|
|
|
|
|
* to a multiple of the APB domain clock PCLK{1,2} (2 if TIMPRE=0, 4 if
|
|
|
|
|
* TIMPRE=1).
|
2020-03-07 17:58:35 +01:00
|
|
|
|
*/
|
2020-10-16 20:07:27 +02:00
|
|
|
|
|
2020-03-07 17:58:35 +01:00
|
|
|
|
if (LL_RCC_GetTIMPrescaler() == LL_RCC_TIM_PRESCALER_TWICE) {
|
2020-10-16 20:07:27 +02:00
|
|
|
|
/* TIMPRE = 0 */
|
|
|
|
|
if (apb_psc <= 2u) {
|
|
|
|
|
LL_RCC_ClocksTypeDef clocks;
|
|
|
|
|
|
|
|
|
|
LL_RCC_GetSystemClocksFreq(&clocks);
|
|
|
|
|
*tim_clk = clocks.HCLK_Frequency;
|
2020-03-07 17:58:35 +01:00
|
|
|
|
} else {
|
2020-04-21 21:50:03 +02:00
|
|
|
|
*tim_clk = bus_clk * 2u;
|
2020-03-07 17:58:35 +01:00
|
|
|
|
}
|
|
|
|
|
} else {
|
2020-10-16 20:07:27 +02:00
|
|
|
|
/* TIMPRE = 1 */
|
|
|
|
|
if (apb_psc <= 4u) {
|
|
|
|
|
LL_RCC_ClocksTypeDef clocks;
|
|
|
|
|
|
|
|
|
|
LL_RCC_GetSystemClocksFreq(&clocks);
|
|
|
|
|
*tim_clk = clocks.HCLK_Frequency;
|
2020-03-07 17:58:35 +01:00
|
|
|
|
} else {
|
2020-04-21 21:50:03 +02:00
|
|
|
|
*tim_clk = bus_clk * 4u;
|
2020-03-07 17:58:35 +01:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#else
|
2017-08-23 00:12:26 +02:00
|
|
|
|
/*
|
|
|
|
|
* If the APB prescaler equals 1, the timer clock frequencies
|
|
|
|
|
* are set to the same frequency as that of the APB domain.
|
|
|
|
|
* Otherwise, they are set to twice (×2) the frequency of the
|
|
|
|
|
* APB domain.
|
|
|
|
|
*/
|
2020-04-21 21:50:03 +02:00
|
|
|
|
if (apb_psc == 1u) {
|
|
|
|
|
*tim_clk = bus_clk;
|
|
|
|
|
} else {
|
|
|
|
|
*tim_clk = bus_clk * 2u;
|
2017-01-24 11:09:06 +01:00
|
|
|
|
}
|
2020-03-07 17:58:35 +01:00
|
|
|
|
#endif
|
2017-01-24 11:09:06 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
return 0;
|
2017-01-24 11:09:06 +01:00
|
|
|
|
}
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2022-04-01 11:06:43 +02:00
|
|
|
|
static int pwm_stm32_set_cycles(const struct device *dev, uint32_t channel,
|
|
|
|
|
uint32_t period_cycles, uint32_t pulse_cycles,
|
|
|
|
|
pwm_flags_t flags)
|
2016-11-25 17:21:26 +01:00
|
|
|
|
{
|
2020-10-02 10:16:24 +02:00
|
|
|
|
const struct pwm_stm32_config *cfg = dev->config;
|
2020-04-21 21:50:03 +02:00
|
|
|
|
|
2022-04-04 16:35:22 +02:00
|
|
|
|
uint32_t ll_channel;
|
|
|
|
|
uint32_t current_ll_channel; /* complementary output if used */
|
drivers: pwm: pwm_stm32: Add 6-PWM support
User can use 6-PWM motor driver in dts like this below:
```dts
pwms =
// ch1,ch2,ch3,ch1n,ch2n,ch3n
<&pwm 1 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch1
<&pwm 2 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch2
<&pwm 3 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch3
<&pwm 1 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 2 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 3 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>;
```
Signed-off-by: Savent Gate <savent_gate@outlook.com>
2023-04-28 15:33:04 +02:00
|
|
|
|
uint32_t negative_ll_channel;
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2022-04-04 16:35:22 +02:00
|
|
|
|
if (channel < 1u || channel > TIMER_MAX_CH) {
|
|
|
|
|
LOG_ERR("Invalid channel (%d)", channel);
|
2016-11-25 17:21:26 +01:00
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
/*
|
|
|
|
|
* Non 32-bit timers count from 0 up to the value in the ARR register
|
|
|
|
|
* (16-bit). Thus period_cycles cannot be greater than UINT16_MAX + 1.
|
|
|
|
|
*/
|
|
|
|
|
if (!IS_TIM_32B_COUNTER_INSTANCE(cfg->timer) &&
|
|
|
|
|
(period_cycles > UINT16_MAX + 1)) {
|
2016-11-25 17:21:26 +01:00
|
|
|
|
return -ENOTSUP;
|
|
|
|
|
}
|
|
|
|
|
|
2021-10-26 15:08:30 +02:00
|
|
|
|
#ifdef CONFIG_PWM_CAPTURE
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (LL_TIM_IsEnabledIT_CC1(cfg->timer) || LL_TIM_IsEnabledIT_CC2(cfg->timer) ||
|
|
|
|
|
LL_TIM_IsEnabledIT_CC3(cfg->timer) || LL_TIM_IsEnabledIT_CC4(cfg->timer)) {
|
|
|
|
|
LOG_ERR("Cannot set PWM output, capture in progress");
|
|
|
|
|
return -EBUSY;
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PWM_CAPTURE */
|
|
|
|
|
|
2022-04-04 16:35:22 +02:00
|
|
|
|
ll_channel = ch2ll[channel - 1u];
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
drivers: pwm: pwm_stm32: Add 6-PWM support
User can use 6-PWM motor driver in dts like this below:
```dts
pwms =
// ch1,ch2,ch3,ch1n,ch2n,ch3n
<&pwm 1 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch1
<&pwm 2 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch2
<&pwm 3 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch3
<&pwm 1 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 2 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 3 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>;
```
Signed-off-by: Savent Gate <savent_gate@outlook.com>
2023-04-28 15:33:04 +02:00
|
|
|
|
if (channel <= ARRAY_SIZE(ch2ll_n)) {
|
|
|
|
|
negative_ll_channel = ch2ll_n[channel - 1u];
|
|
|
|
|
} else {
|
|
|
|
|
negative_ll_channel = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2022-01-25 10:49:28 +01:00
|
|
|
|
/* in LL_TIM_CC_DisableChannel and LL_TIM_CC_IsEnabledChannel,
|
|
|
|
|
* the channel param could be the complementary one
|
|
|
|
|
*/
|
2023-01-04 16:30:00 +01:00
|
|
|
|
if ((flags & STM32_PWM_COMPLEMENTARY_MASK) == STM32_PWM_COMPLEMENTARY) {
|
drivers: pwm: pwm_stm32: Add 6-PWM support
User can use 6-PWM motor driver in dts like this below:
```dts
pwms =
// ch1,ch2,ch3,ch1n,ch2n,ch3n
<&pwm 1 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch1
<&pwm 2 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch2
<&pwm 3 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch3
<&pwm 1 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 2 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 3 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>;
```
Signed-off-by: Savent Gate <savent_gate@outlook.com>
2023-04-28 15:33:04 +02:00
|
|
|
|
if (!negative_ll_channel) {
|
2022-01-25 10:49:28 +01:00
|
|
|
|
/* setting a flag on a channel that has not this capability */
|
2022-04-04 16:35:22 +02:00
|
|
|
|
LOG_ERR("Channel %d has NO complementary output", channel);
|
2022-01-25 10:49:28 +01:00
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
drivers: pwm: pwm_stm32: Add 6-PWM support
User can use 6-PWM motor driver in dts like this below:
```dts
pwms =
// ch1,ch2,ch3,ch1n,ch2n,ch3n
<&pwm 1 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch1
<&pwm 2 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch2
<&pwm 3 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch3
<&pwm 1 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 2 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 3 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>;
```
Signed-off-by: Savent Gate <savent_gate@outlook.com>
2023-04-28 15:33:04 +02:00
|
|
|
|
current_ll_channel = negative_ll_channel;
|
2022-01-25 10:49:28 +01:00
|
|
|
|
} else {
|
2022-04-04 16:35:22 +02:00
|
|
|
|
current_ll_channel = ll_channel;
|
2022-01-25 10:49:28 +01:00
|
|
|
|
}
|
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
if (period_cycles == 0u) {
|
2022-04-04 16:35:22 +02:00
|
|
|
|
LL_TIM_CC_DisableChannel(cfg->timer, current_ll_channel);
|
2020-04-21 21:50:03 +02:00
|
|
|
|
return 0;
|
2016-11-25 17:21:26 +01:00
|
|
|
|
}
|
|
|
|
|
|
2022-05-05 12:12:36 +02:00
|
|
|
|
if (cfg->countermode == LL_TIM_COUNTERMODE_UP) {
|
|
|
|
|
/* remove 1 period cycle, accounts for 1 extra low cycle */
|
|
|
|
|
period_cycles -= 1U;
|
|
|
|
|
} else if (cfg->countermode == LL_TIM_COUNTERMODE_DOWN) {
|
|
|
|
|
/* remove 1 pulse cycle, accounts for 1 extra high cycle */
|
|
|
|
|
pulse_cycles -= 1U;
|
|
|
|
|
/* remove 1 period cycle, accounts for 1 extra low cycle */
|
|
|
|
|
period_cycles -= 1U;
|
|
|
|
|
} else if (is_center_aligned(cfg->countermode)) {
|
|
|
|
|
pulse_cycles /= 2U;
|
|
|
|
|
period_cycles /= 2U;
|
|
|
|
|
} else {
|
|
|
|
|
return -ENOTSUP;
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-04 16:35:22 +02:00
|
|
|
|
if (!LL_TIM_CC_IsEnabledChannel(cfg->timer, current_ll_channel)) {
|
2020-04-21 21:50:03 +02:00
|
|
|
|
LL_TIM_OC_InitTypeDef oc_init;
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
LL_TIM_OC_StructInit(&oc_init);
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
oc_init.OCMode = LL_TIM_OCMODE_PWM1;
|
2022-01-25 10:49:28 +01:00
|
|
|
|
|
|
|
|
|
#if defined(LL_TIM_CHANNEL_CH1N)
|
2023-01-04 16:30:00 +01:00
|
|
|
|
/* the flags holds the STM32_PWM_COMPLEMENTARY information */
|
|
|
|
|
if ((flags & STM32_PWM_COMPLEMENTARY_MASK) == STM32_PWM_COMPLEMENTARY) {
|
2022-01-25 10:49:28 +01:00
|
|
|
|
oc_init.OCNState = LL_TIM_OCSTATE_ENABLE;
|
|
|
|
|
oc_init.OCNPolarity = get_polarity(flags);
|
drivers: pwm: pwm_stm32: Add 6-PWM support
User can use 6-PWM motor driver in dts like this below:
```dts
pwms =
// ch1,ch2,ch3,ch1n,ch2n,ch3n
<&pwm 1 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch1
<&pwm 2 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch2
<&pwm 3 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch3
<&pwm 1 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 2 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 3 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>;
```
Signed-off-by: Savent Gate <savent_gate@outlook.com>
2023-04-28 15:33:04 +02:00
|
|
|
|
|
|
|
|
|
/* inherit the polarity of the positive output */
|
|
|
|
|
oc_init.OCState = LL_TIM_CC_IsEnabledChannel(cfg->timer, ll_channel)
|
|
|
|
|
? LL_TIM_OCSTATE_ENABLE
|
|
|
|
|
: LL_TIM_OCSTATE_DISABLE;
|
|
|
|
|
oc_init.OCPolarity = LL_TIM_OC_GetPolarity(cfg->timer, ll_channel);
|
2022-01-25 10:49:28 +01:00
|
|
|
|
} else {
|
|
|
|
|
oc_init.OCState = LL_TIM_OCSTATE_ENABLE;
|
|
|
|
|
oc_init.OCPolarity = get_polarity(flags);
|
drivers: pwm: pwm_stm32: Add 6-PWM support
User can use 6-PWM motor driver in dts like this below:
```dts
pwms =
// ch1,ch2,ch3,ch1n,ch2n,ch3n
<&pwm 1 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch1
<&pwm 2 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch2
<&pwm 3 PWM_USEC(50) PWM_POLARITY_NORMAL>, // ch3
<&pwm 1 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 2 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>,
<&pwm 3 PWM_USEC(50) (PWM_POLARITY_NORMAL|STM32_PWM_COMPLEMENTARY)>;
```
Signed-off-by: Savent Gate <savent_gate@outlook.com>
2023-04-28 15:33:04 +02:00
|
|
|
|
|
|
|
|
|
/* inherit the polarity of the negative output */
|
|
|
|
|
if (negative_ll_channel) {
|
|
|
|
|
oc_init.OCNState =
|
|
|
|
|
LL_TIM_CC_IsEnabledChannel(cfg->timer, negative_ll_channel)
|
|
|
|
|
? LL_TIM_OCSTATE_ENABLE
|
|
|
|
|
: LL_TIM_OCSTATE_DISABLE;
|
|
|
|
|
oc_init.OCNPolarity =
|
|
|
|
|
LL_TIM_OC_GetPolarity(cfg->timer, negative_ll_channel);
|
|
|
|
|
}
|
2022-01-25 10:49:28 +01:00
|
|
|
|
}
|
|
|
|
|
#else /* LL_TIM_CHANNEL_CH1N */
|
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
oc_init.OCState = LL_TIM_OCSTATE_ENABLE;
|
2020-04-23 16:10:12 +02:00
|
|
|
|
oc_init.OCPolarity = get_polarity(flags);
|
2022-01-25 10:49:28 +01:00
|
|
|
|
#endif /* LL_TIM_CHANNEL_CH1N */
|
|
|
|
|
oc_init.CompareValue = pulse_cycles;
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2021-10-26 15:08:30 +02:00
|
|
|
|
#ifdef CONFIG_PWM_CAPTURE
|
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(cfg->timer)) {
|
|
|
|
|
LL_TIM_SetSlaveMode(cfg->timer,
|
|
|
|
|
LL_TIM_SLAVEMODE_DISABLED);
|
|
|
|
|
LL_TIM_SetTriggerInput(cfg->timer, LL_TIM_TS_ITR0);
|
|
|
|
|
LL_TIM_DisableMasterSlaveMode(cfg->timer);
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PWM_CAPTURE */
|
|
|
|
|
|
2022-01-25 10:49:28 +01:00
|
|
|
|
/* in LL_TIM_OC_Init, the channel is always the non-complementary */
|
2022-04-04 16:35:22 +02:00
|
|
|
|
if (LL_TIM_OC_Init(cfg->timer, ll_channel, &oc_init) != SUCCESS) {
|
2020-04-21 21:50:03 +02:00
|
|
|
|
LOG_ERR("Could not initialize timer channel output");
|
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2020-10-28 17:50:33 +01:00
|
|
|
|
LL_TIM_EnableARRPreload(cfg->timer);
|
2022-01-25 10:49:28 +01:00
|
|
|
|
/* in LL_TIM_OC_EnablePreload, the channel is always the non-complementary */
|
2022-04-04 16:35:22 +02:00
|
|
|
|
LL_TIM_OC_EnablePreload(cfg->timer, ll_channel);
|
2022-04-11 11:50:22 +02:00
|
|
|
|
LL_TIM_SetAutoReload(cfg->timer, period_cycles);
|
2020-10-28 17:50:33 +01:00
|
|
|
|
LL_TIM_GenerateEvent_UPDATE(cfg->timer);
|
2020-04-21 21:50:03 +02:00
|
|
|
|
} else {
|
2022-01-25 10:49:28 +01:00
|
|
|
|
/* in LL_TIM_OC_SetPolarity, the channel could be the complementary one */
|
2022-04-04 16:35:22 +02:00
|
|
|
|
LL_TIM_OC_SetPolarity(cfg->timer, current_ll_channel, get_polarity(flags));
|
|
|
|
|
set_timer_compare[channel - 1u](cfg->timer, pulse_cycles);
|
2022-04-11 11:50:22 +02:00
|
|
|
|
LL_TIM_SetAutoReload(cfg->timer, period_cycles);
|
2020-04-21 21:50:03 +02:00
|
|
|
|
}
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
return 0;
|
2016-11-25 17:21:26 +01:00
|
|
|
|
}
|
|
|
|
|
|
2021-10-26 15:08:30 +02:00
|
|
|
|
#ifdef CONFIG_PWM_CAPTURE
|
2023-06-01 08:29:59 +02:00
|
|
|
|
static int init_capture_channels(const struct device *dev, uint32_t channel,
|
|
|
|
|
pwm_flags_t flags)
|
2021-10-26 15:08:30 +02:00
|
|
|
|
{
|
|
|
|
|
const struct pwm_stm32_config *cfg = dev->config;
|
|
|
|
|
bool is_inverted = (flags & PWM_POLARITY_MASK) == PWM_POLARITY_INVERTED;
|
|
|
|
|
LL_TIM_IC_InitTypeDef ic;
|
|
|
|
|
|
|
|
|
|
LL_TIM_IC_StructInit(&ic);
|
|
|
|
|
ic.ICPrescaler = TIM_ICPSC_DIV1;
|
|
|
|
|
ic.ICFilter = LL_TIM_IC_FILTER_FDIV1;
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
/* Setup main channel */
|
|
|
|
|
ic.ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
|
|
|
|
|
ic.ICPolarity = is_inverted ? LL_TIM_IC_POLARITY_FALLING : LL_TIM_IC_POLARITY_RISING;
|
|
|
|
|
|
|
|
|
|
if (LL_TIM_IC_Init(cfg->timer, ch2ll[channel - 1], &ic) != SUCCESS) {
|
|
|
|
|
LOG_ERR("Could not initialize main channel for PWM capture");
|
|
|
|
|
return -EIO;
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
/* Setup complimentary channel */
|
|
|
|
|
ic.ICActiveInput = LL_TIM_ACTIVEINPUT_INDIRECTTI;
|
|
|
|
|
ic.ICPolarity = is_inverted ? LL_TIM_IC_POLARITY_RISING : LL_TIM_IC_POLARITY_FALLING;
|
|
|
|
|
|
|
|
|
|
if (LL_TIM_IC_Init(cfg->timer, ch2ll[complimentary_channel[channel] - 1], &ic) != SUCCESS) {
|
|
|
|
|
LOG_ERR("Could not initialize complimentary channel for PWM capture");
|
2021-10-26 15:08:30 +02:00
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-01 11:06:43 +02:00
|
|
|
|
static int pwm_stm32_configure_capture(const struct device *dev,
|
|
|
|
|
uint32_t channel, pwm_flags_t flags,
|
|
|
|
|
pwm_capture_callback_handler_t cb,
|
|
|
|
|
void *user_data)
|
2021-10-26 15:08:30 +02:00
|
|
|
|
{
|
|
|
|
|
/*
|
2023-06-01 08:29:59 +02:00
|
|
|
|
* Capture is implemented in two different ways, depending on the
|
|
|
|
|
* four-channel-capture-support setting in the node.
|
|
|
|
|
* - Two Channel Support:
|
|
|
|
|
* Only two channels (1 and 2) are available for capture. It uses
|
|
|
|
|
* the slave mode controller to reset the counter on each edge.
|
|
|
|
|
* - Four Channel Support:
|
|
|
|
|
* All four channels are available for capture. Instead of the
|
|
|
|
|
* slave mode controller it uses the ISR to reset the counter.
|
|
|
|
|
* This is slightly less accurate, but still within acceptable
|
|
|
|
|
* bounds.
|
2021-10-26 15:08:30 +02:00
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
const struct pwm_stm32_config *cfg = dev->config;
|
|
|
|
|
struct pwm_stm32_data *data = dev->data;
|
|
|
|
|
struct pwm_stm32_capture_data *cpt = &data->capture;
|
|
|
|
|
int ret;
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (!cfg->four_channel_capture_support) {
|
|
|
|
|
if ((channel != 1u) && (channel != 2u)) {
|
|
|
|
|
LOG_ERR("PWM capture only supported on first two channels");
|
|
|
|
|
return -ENOTSUP;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if ((channel < 1u) || (channel > 4u)) {
|
|
|
|
|
LOG_ERR("PWM capture only exists on channels 1, 2, 3 and 4.");
|
|
|
|
|
return -ENOTSUP;
|
|
|
|
|
}
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (LL_TIM_IsEnabledIT_CC1(cfg->timer) || LL_TIM_IsEnabledIT_CC2(cfg->timer) ||
|
|
|
|
|
LL_TIM_IsEnabledIT_CC3(cfg->timer) || LL_TIM_IsEnabledIT_CC4(cfg->timer)) {
|
|
|
|
|
LOG_ERR("PWM capture already in progress");
|
2021-10-26 15:08:30 +02:00
|
|
|
|
return -EBUSY;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!(flags & PWM_CAPTURE_TYPE_MASK)) {
|
|
|
|
|
LOG_ERR("No PWM capture type specified");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (!cfg->four_channel_capture_support && !IS_TIM_SLAVE_INSTANCE(cfg->timer)) {
|
|
|
|
|
/* slave mode is only used when not in four channel mode */
|
2021-10-26 15:08:30 +02:00
|
|
|
|
LOG_ERR("Timer does not support slave mode for PWM capture");
|
|
|
|
|
return -ENOTSUP;
|
|
|
|
|
}
|
|
|
|
|
|
2022-03-17 13:48:38 +01:00
|
|
|
|
cpt->callback = cb; /* even if the cb is reset, this is not an error */
|
2021-10-26 15:08:30 +02:00
|
|
|
|
cpt->user_data = user_data;
|
|
|
|
|
cpt->capture_period = (flags & PWM_CAPTURE_TYPE_PERIOD) ? true : false;
|
|
|
|
|
cpt->capture_pulse = (flags & PWM_CAPTURE_TYPE_PULSE) ? true : false;
|
|
|
|
|
cpt->continuous = (flags & PWM_CAPTURE_MODE_CONTINUOUS) ? true : false;
|
|
|
|
|
|
|
|
|
|
/* Prevents faulty behavior while making changes */
|
|
|
|
|
LL_TIM_SetSlaveMode(cfg->timer, LL_TIM_SLAVEMODE_DISABLED);
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
ret = init_capture_channels(dev, channel, flags);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
if (ret < 0) {
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (!cfg->four_channel_capture_support) {
|
|
|
|
|
if (channel == 1u) {
|
|
|
|
|
LL_TIM_SetTriggerInput(cfg->timer, LL_TIM_TS_TI1FP1);
|
|
|
|
|
} else {
|
|
|
|
|
LL_TIM_SetTriggerInput(cfg->timer, LL_TIM_TS_TI2FP2);
|
|
|
|
|
}
|
|
|
|
|
LL_TIM_SetSlaveMode(cfg->timer, LL_TIM_SLAVEMODE_RESET);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
LL_TIM_EnableARRPreload(cfg->timer);
|
|
|
|
|
if (!IS_TIM_32B_COUNTER_INSTANCE(cfg->timer)) {
|
|
|
|
|
LL_TIM_SetAutoReload(cfg->timer, 0xffffu);
|
|
|
|
|
} else {
|
|
|
|
|
LL_TIM_SetAutoReload(cfg->timer, 0xffffffffu);
|
|
|
|
|
}
|
|
|
|
|
LL_TIM_EnableUpdateEvent(cfg->timer);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-01 11:06:43 +02:00
|
|
|
|
static int pwm_stm32_enable_capture(const struct device *dev, uint32_t channel)
|
2021-10-26 15:08:30 +02:00
|
|
|
|
{
|
|
|
|
|
const struct pwm_stm32_config *cfg = dev->config;
|
|
|
|
|
struct pwm_stm32_data *data = dev->data;
|
2023-06-01 08:29:59 +02:00
|
|
|
|
struct pwm_stm32_capture_data *cpt = &data->capture;
|
2021-10-26 15:08:30 +02:00
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (!cfg->four_channel_capture_support) {
|
|
|
|
|
if ((channel != 1u) && (channel != 2u)) {
|
|
|
|
|
LOG_ERR("PWM capture only supported on first two channels");
|
|
|
|
|
return -ENOTSUP;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if ((channel < 1u) || (channel > 4u)) {
|
|
|
|
|
LOG_ERR("PWM capture only exists on channels 1, 2, 3 and 4.");
|
|
|
|
|
return -ENOTSUP;
|
|
|
|
|
}
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (LL_TIM_IsEnabledIT_CC1(cfg->timer) || LL_TIM_IsEnabledIT_CC2(cfg->timer) ||
|
|
|
|
|
LL_TIM_IsEnabledIT_CC3(cfg->timer) || LL_TIM_IsEnabledIT_CC4(cfg->timer)) {
|
2021-10-26 15:08:30 +02:00
|
|
|
|
LOG_ERR("PWM capture already active");
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
}
|
|
|
|
|
|
2022-03-17 13:48:38 +01:00
|
|
|
|
if (!data->capture.callback) {
|
|
|
|
|
LOG_ERR("PWM capture not configured");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
cpt->channel = channel;
|
|
|
|
|
cpt->state = CAPTURE_STATE_WAIT_FOR_PULSE_START;
|
|
|
|
|
data->capture.skip_irq = cfg->four_channel_capture_support ? 0 : SKIPPED_PWM_CAPTURES;
|
2021-10-26 15:08:30 +02:00
|
|
|
|
data->capture.overflows = 0u;
|
2023-06-01 08:29:59 +02:00
|
|
|
|
|
|
|
|
|
clear_capture_interrupt[channel - 1](cfg->timer);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
LL_TIM_ClearFlag_UPDATE(cfg->timer);
|
|
|
|
|
|
|
|
|
|
LL_TIM_SetUpdateSource(cfg->timer, LL_TIM_UPDATESOURCE_COUNTER);
|
2023-06-01 08:29:59 +02:00
|
|
|
|
|
|
|
|
|
enable_capture_interrupt[channel - 1](cfg->timer);
|
|
|
|
|
|
|
|
|
|
LL_TIM_CC_EnableChannel(cfg->timer, ch2ll[channel - 1]);
|
|
|
|
|
LL_TIM_CC_EnableChannel(cfg->timer, ch2ll[complimentary_channel[channel] - 1]);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
LL_TIM_EnableIT_UPDATE(cfg->timer);
|
2023-06-01 08:29:59 +02:00
|
|
|
|
LL_TIM_GenerateEvent_UPDATE(cfg->timer);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-01 11:06:43 +02:00
|
|
|
|
static int pwm_stm32_disable_capture(const struct device *dev, uint32_t channel)
|
2021-10-26 15:08:30 +02:00
|
|
|
|
{
|
|
|
|
|
const struct pwm_stm32_config *cfg = dev->config;
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (!cfg->four_channel_capture_support) {
|
|
|
|
|
if ((channel != 1u) && (channel != 2u)) {
|
|
|
|
|
LOG_ERR("PWM capture only supported on first two channels");
|
|
|
|
|
return -ENOTSUP;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if ((channel < 1u) || (channel > 4u)) {
|
|
|
|
|
LOG_ERR("PWM capture only exists on channels 1, 2, 3 and 4.");
|
|
|
|
|
return -ENOTSUP;
|
|
|
|
|
}
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
LL_TIM_SetUpdateSource(cfg->timer, LL_TIM_UPDATESOURCE_REGULAR);
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
disable_capture_interrupt[channel - 1](cfg->timer);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
LL_TIM_DisableIT_UPDATE(cfg->timer);
|
|
|
|
|
LL_TIM_CC_DisableChannel(cfg->timer, ch2ll[channel - 1]);
|
|
|
|
|
LL_TIM_CC_DisableChannel(cfg->timer, ch2ll[complimentary_channel[channel] - 1]);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
return 0;
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void pwm_stm32_isr(const struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
const struct pwm_stm32_config *cfg = dev->config;
|
|
|
|
|
struct pwm_stm32_data *data = dev->data;
|
|
|
|
|
struct pwm_stm32_capture_data *cpt = &data->capture;
|
|
|
|
|
int status = 0;
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (cpt->skip_irq != 0u) {
|
2021-10-26 15:08:30 +02:00
|
|
|
|
if (LL_TIM_IsActiveFlag_UPDATE(cfg->timer)) {
|
|
|
|
|
LL_TIM_ClearFlag_UPDATE(cfg->timer);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (LL_TIM_IsActiveFlag_CC1(cfg->timer)
|
2023-06-01 08:29:59 +02:00
|
|
|
|
|| LL_TIM_IsActiveFlag_CC2(cfg->timer)
|
|
|
|
|
|| LL_TIM_IsActiveFlag_CC3(cfg->timer)
|
|
|
|
|
|| LL_TIM_IsActiveFlag_CC4(cfg->timer)) {
|
2021-10-26 15:08:30 +02:00
|
|
|
|
LL_TIM_ClearFlag_CC1(cfg->timer);
|
|
|
|
|
LL_TIM_ClearFlag_CC2(cfg->timer);
|
2023-06-01 08:29:59 +02:00
|
|
|
|
LL_TIM_ClearFlag_CC3(cfg->timer);
|
|
|
|
|
LL_TIM_ClearFlag_CC4(cfg->timer);
|
|
|
|
|
cpt->skip_irq--;
|
|
|
|
|
}
|
2021-10-26 15:08:30 +02:00
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
return;
|
|
|
|
|
}
|
2021-10-26 15:08:30 +02:00
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (LL_TIM_IsActiveFlag_UPDATE(cfg->timer)) {
|
|
|
|
|
LL_TIM_ClearFlag_UPDATE(cfg->timer);
|
|
|
|
|
if (cfg->four_channel_capture_support &&
|
|
|
|
|
cpt->state == CAPTURE_STATE_WAIT_FOR_UPDATE_EVENT) {
|
|
|
|
|
/* Special handling of UPDATE event in case it's triggered */
|
|
|
|
|
cpt->state = CAPTURE_STATE_WAIT_FOR_PERIOD_END;
|
|
|
|
|
} else {
|
|
|
|
|
cpt->overflows++;
|
|
|
|
|
}
|
|
|
|
|
}
|
2021-10-26 15:08:30 +02:00
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (!cfg->four_channel_capture_support) {
|
|
|
|
|
if (is_capture_active[cpt->channel - 1](cfg->timer) ||
|
|
|
|
|
is_capture_active[complimentary_channel[cpt->channel] - 1](cfg->timer)) {
|
|
|
|
|
clear_capture_interrupt[cpt->channel - 1](cfg->timer);
|
|
|
|
|
clear_capture_interrupt
|
|
|
|
|
[complimentary_channel[cpt->channel] - 1](cfg->timer);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
cpt->period = get_channel_capture[cpt->channel - 1](cfg->timer);
|
|
|
|
|
cpt->pulse = get_channel_capture
|
|
|
|
|
[complimentary_channel[cpt->channel] - 1](cfg->timer);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
|
|
|
|
} else {
|
2023-06-01 08:29:59 +02:00
|
|
|
|
if (cpt->state == CAPTURE_STATE_WAIT_FOR_PULSE_START &&
|
|
|
|
|
is_capture_active[cpt->channel - 1](cfg->timer)) {
|
|
|
|
|
/* Reset the counter manually instead of automatically by HW
|
|
|
|
|
* This sets the pulse-start at 0 and makes the pulse-end
|
|
|
|
|
* and period related to that number. Sure we loose some
|
|
|
|
|
* accuracy but it's within acceptable range.
|
|
|
|
|
*
|
|
|
|
|
* This is done through an UPDATE event to also reset
|
|
|
|
|
* the prescalar. This could look like an overflow event
|
|
|
|
|
* and might therefore require special handling.
|
|
|
|
|
*/
|
|
|
|
|
cpt->state = CAPTURE_STATE_WAIT_FOR_UPDATE_EVENT;
|
|
|
|
|
LL_TIM_GenerateEvent_UPDATE(cfg->timer);
|
|
|
|
|
|
|
|
|
|
} else if ((cpt->state == CAPTURE_STATE_WAIT_FOR_UPDATE_EVENT ||
|
|
|
|
|
cpt->state == CAPTURE_STATE_WAIT_FOR_PERIOD_END) &&
|
|
|
|
|
is_capture_active[cpt->channel - 1](cfg->timer)) {
|
|
|
|
|
cpt->state = CAPTURE_STATE_IDLE;
|
|
|
|
|
/* The end of the period. Both capture channels should now contain
|
|
|
|
|
* the timer value when the pulse and period ended respectively.
|
|
|
|
|
*/
|
|
|
|
|
cpt->pulse = get_channel_capture[complimentary_channel[cpt->channel] - 1]
|
|
|
|
|
(cfg->timer);
|
|
|
|
|
cpt->period = get_channel_capture[cpt->channel - 1](cfg->timer);
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
|
|
|
|
|
2023-06-01 08:29:59 +02:00
|
|
|
|
clear_capture_interrupt[cpt->channel - 1](cfg->timer);
|
|
|
|
|
|
|
|
|
|
if (cpt->state != CAPTURE_STATE_IDLE) {
|
|
|
|
|
/* Still waiting for a complete capture */
|
|
|
|
|
return;
|
|
|
|
|
}
|
2023-12-21 15:27:42 +01:00
|
|
|
|
}
|
2023-06-01 08:29:59 +02:00
|
|
|
|
|
2023-12-21 15:27:42 +01:00
|
|
|
|
if (cpt->overflows) {
|
|
|
|
|
LOG_ERR("counter overflow during PWM capture");
|
|
|
|
|
status = -ERANGE;
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
2023-06-01 08:29:59 +02:00
|
|
|
|
|
|
|
|
|
if (!cpt->continuous) {
|
|
|
|
|
pwm_stm32_disable_capture(dev, cpt->channel);
|
|
|
|
|
} else {
|
|
|
|
|
cpt->overflows = 0u;
|
|
|
|
|
cpt->state = CAPTURE_STATE_WAIT_FOR_PULSE_START;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cpt->callback != NULL) {
|
|
|
|
|
cpt->callback(dev, cpt->channel, cpt->capture_period ? cpt->period : 0u,
|
|
|
|
|
cpt->capture_pulse ? cpt->pulse : 0u, status, cpt->user_data);
|
|
|
|
|
}
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
2023-06-01 08:29:59 +02:00
|
|
|
|
|
2021-10-26 15:08:30 +02:00
|
|
|
|
#endif /* CONFIG_PWM_CAPTURE */
|
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
|
static int pwm_stm32_get_cycles_per_sec(const struct device *dev,
|
2022-04-04 16:35:22 +02:00
|
|
|
|
uint32_t channel, uint64_t *cycles)
|
2016-11-25 17:21:26 +01:00
|
|
|
|
{
|
2020-10-02 10:16:24 +02:00
|
|
|
|
struct pwm_stm32_data *data = dev->data;
|
|
|
|
|
const struct pwm_stm32_config *cfg = dev->config;
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
*cycles = (uint64_t)(data->tim_clk / (cfg->prescaler + 1));
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
static const struct pwm_driver_api pwm_stm32_driver_api = {
|
2022-04-01 11:06:43 +02:00
|
|
|
|
.set_cycles = pwm_stm32_set_cycles,
|
2016-11-25 17:21:26 +01:00
|
|
|
|
.get_cycles_per_sec = pwm_stm32_get_cycles_per_sec,
|
2021-10-26 15:08:30 +02:00
|
|
|
|
#ifdef CONFIG_PWM_CAPTURE
|
2022-04-01 11:06:43 +02:00
|
|
|
|
.configure_capture = pwm_stm32_configure_capture,
|
|
|
|
|
.enable_capture = pwm_stm32_enable_capture,
|
|
|
|
|
.disable_capture = pwm_stm32_disable_capture,
|
2021-10-26 15:08:30 +02:00
|
|
|
|
#endif /* CONFIG_PWM_CAPTURE */
|
2016-11-25 17:21:26 +01:00
|
|
|
|
};
|
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
|
static int pwm_stm32_init(const struct device *dev)
|
2016-11-25 17:21:26 +01:00
|
|
|
|
{
|
2020-10-02 10:16:24 +02:00
|
|
|
|
struct pwm_stm32_data *data = dev->data;
|
|
|
|
|
const struct pwm_stm32_config *cfg = dev->config;
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
int r;
|
2020-04-30 20:33:38 +02:00
|
|
|
|
const struct device *clk;
|
2020-04-21 21:50:03 +02:00
|
|
|
|
LL_TIM_InitTypeDef init;
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
/* enable clock and store its speed */
|
2021-02-11 18:49:24 +01:00
|
|
|
|
clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2022-08-08 16:04:22 +02:00
|
|
|
|
if (!device_is_ready(clk)) {
|
|
|
|
|
LOG_ERR("clock control device not ready");
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
2023-03-28 08:24:07 +02:00
|
|
|
|
r = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken);
|
2020-04-21 21:50:03 +02:00
|
|
|
|
if (r < 0) {
|
|
|
|
|
LOG_ERR("Could not initialize clock (%d)", r);
|
|
|
|
|
return r;
|
|
|
|
|
}
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
r = get_tim_clk(&cfg->pclken, &data->tim_clk);
|
|
|
|
|
if (r < 0) {
|
|
|
|
|
LOG_ERR("Could not obtain timer clock (%d)", r);
|
|
|
|
|
return r;
|
|
|
|
|
}
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2023-06-23 08:24:07 +02:00
|
|
|
|
/* Reset timer to default state using RCC */
|
|
|
|
|
(void)reset_line_toggle_dt(&data->reset);
|
|
|
|
|
|
2020-10-02 10:54:40 +02:00
|
|
|
|
/* configure pinmux */
|
2021-11-08 11:42:44 +01:00
|
|
|
|
r = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
|
2020-10-16 17:20:00 +02:00
|
|
|
|
if (r < 0) {
|
|
|
|
|
LOG_ERR("PWM pinctrl setup failed (%d)", r);
|
|
|
|
|
return r;
|
2020-10-02 10:54:40 +02:00
|
|
|
|
}
|
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
/* initialize timer */
|
|
|
|
|
LL_TIM_StructInit(&init);
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
init.Prescaler = cfg->prescaler;
|
2022-04-11 11:50:22 +02:00
|
|
|
|
init.CounterMode = cfg->countermode;
|
2020-04-21 21:50:03 +02:00
|
|
|
|
init.Autoreload = 0u;
|
|
|
|
|
init.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
|
2020-12-15 15:19:39 +01:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
if (LL_TIM_Init(cfg->timer, &init) != SUCCESS) {
|
|
|
|
|
LOG_ERR("Could not initialize timer");
|
2018-12-07 11:09:28 +01:00
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
2016-11-25 17:21:26 +01:00
|
|
|
|
|
2021-04-20 13:01:27 +02:00
|
|
|
|
#if !defined(CONFIG_SOC_SERIES_STM32L0X) && !defined(CONFIG_SOC_SERIES_STM32L1X)
|
2020-04-21 21:50:03 +02:00
|
|
|
|
/* enable outputs and counter */
|
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(cfg->timer)) {
|
|
|
|
|
LL_TIM_EnableAllOutputs(cfg->timer);
|
|
|
|
|
}
|
2020-12-15 15:19:39 +01:00
|
|
|
|
#endif
|
2020-04-21 21:50:03 +02:00
|
|
|
|
|
|
|
|
|
LL_TIM_EnableCounter(cfg->timer);
|
|
|
|
|
|
2021-10-26 15:08:30 +02:00
|
|
|
|
#ifdef CONFIG_PWM_CAPTURE
|
|
|
|
|
cfg->irq_config_func(dev);
|
|
|
|
|
#endif /* CONFIG_PWM_CAPTURE */
|
|
|
|
|
|
2016-11-25 17:21:26 +01:00
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-19 14:48:28 +02:00
|
|
|
|
#define PWM(index) DT_INST_PARENT(index)
|
|
|
|
|
|
2021-10-26 15:08:30 +02:00
|
|
|
|
#ifdef CONFIG_PWM_CAPTURE
|
2023-04-26 21:23:22 +02:00
|
|
|
|
#define IRQ_CONNECT_AND_ENABLE_BY_NAME(index, name) \
|
|
|
|
|
{ \
|
2023-07-19 14:48:28 +02:00
|
|
|
|
IRQ_CONNECT(DT_IRQ_BY_NAME(PWM(index), name, irq), \
|
|
|
|
|
DT_IRQ_BY_NAME(PWM(index), name, priority), \
|
2023-04-26 21:23:22 +02:00
|
|
|
|
pwm_stm32_isr, DEVICE_DT_INST_GET(index), 0); \
|
2023-07-19 14:48:28 +02:00
|
|
|
|
irq_enable(DT_IRQ_BY_NAME(PWM(index), name, irq)); \
|
2023-04-26 21:23:22 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define IRQ_CONNECT_AND_ENABLE_DEFAULT(index) \
|
|
|
|
|
{ \
|
2023-07-19 14:48:28 +02:00
|
|
|
|
IRQ_CONNECT(DT_IRQN(PWM(index)), \
|
|
|
|
|
DT_IRQ(PWM(index), priority), \
|
2023-04-26 21:23:22 +02:00
|
|
|
|
pwm_stm32_isr, DEVICE_DT_INST_GET(index), 0); \
|
2023-07-19 14:48:28 +02:00
|
|
|
|
irq_enable(DT_IRQN(PWM(index))); \
|
2023-04-26 21:23:22 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define IRQ_CONFIG_FUNC(index) \
|
|
|
|
|
static void pwm_stm32_irq_config_func_##index(const struct device *dev) \
|
|
|
|
|
{ \
|
2023-07-19 14:48:28 +02:00
|
|
|
|
COND_CODE_1(DT_IRQ_HAS_NAME(PWM(index), cc), \
|
2023-04-26 21:23:22 +02:00
|
|
|
|
(IRQ_CONNECT_AND_ENABLE_BY_NAME(index, cc)), \
|
|
|
|
|
(IRQ_CONNECT_AND_ENABLE_DEFAULT(index)) \
|
|
|
|
|
); \
|
2021-10-26 15:08:30 +02:00
|
|
|
|
}
|
2023-06-01 08:29:59 +02:00
|
|
|
|
#define CAPTURE_INIT(index) \
|
|
|
|
|
.irq_config_func = pwm_stm32_irq_config_func_##index, \
|
|
|
|
|
.four_channel_capture_support = DT_INST_PROP(index, four_channel_capture_support)
|
2021-10-26 15:08:30 +02:00
|
|
|
|
#else
|
|
|
|
|
#define IRQ_CONFIG_FUNC(index)
|
|
|
|
|
#define CAPTURE_INIT(index)
|
|
|
|
|
#endif /* CONFIG_PWM_CAPTURE */
|
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
#define DT_INST_CLK(index, inst) \
|
|
|
|
|
{ \
|
2023-07-19 14:48:28 +02:00
|
|
|
|
.bus = DT_CLOCKS_CELL(PWM(index), bus), \
|
|
|
|
|
.enr = DT_CLOCKS_CELL(PWM(index), bits) \
|
2020-04-21 21:50:03 +02:00
|
|
|
|
}
|
|
|
|
|
|
2023-07-19 14:48:28 +02:00
|
|
|
|
|
2020-04-21 21:50:03 +02:00
|
|
|
|
#define PWM_DEVICE_INIT(index) \
|
2023-06-23 08:24:07 +02:00
|
|
|
|
static struct pwm_stm32_data pwm_stm32_data_##index = { \
|
|
|
|
|
.reset = RESET_DT_SPEC_GET(PWM(index)), \
|
|
|
|
|
}; \
|
|
|
|
|
\
|
2021-10-26 15:08:30 +02:00
|
|
|
|
IRQ_CONFIG_FUNC(index) \
|
2020-04-21 21:50:03 +02:00
|
|
|
|
\
|
2021-12-23 12:33:03 +01:00
|
|
|
|
PINCTRL_DT_INST_DEFINE(index); \
|
2020-10-02 10:54:40 +02:00
|
|
|
|
\
|
2020-04-21 21:50:03 +02:00
|
|
|
|
static const struct pwm_stm32_config pwm_stm32_config_##index = { \
|
2023-07-19 14:48:28 +02:00
|
|
|
|
.timer = (TIM_TypeDef *)DT_REG_ADDR(PWM(index)), \
|
|
|
|
|
.prescaler = DT_PROP(PWM(index), st_prescaler), \
|
|
|
|
|
.countermode = DT_PROP(PWM(index), st_countermode), \
|
2020-10-02 10:54:40 +02:00
|
|
|
|
.pclken = DT_INST_CLK(index, timer), \
|
2021-11-08 11:42:44 +01:00
|
|
|
|
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
|
2021-10-26 15:08:30 +02:00
|
|
|
|
CAPTURE_INIT(index) \
|
2020-04-21 21:50:03 +02:00
|
|
|
|
}; \
|
|
|
|
|
\
|
2021-04-28 11:36:44 +02:00
|
|
|
|
DEVICE_DT_INST_DEFINE(index, &pwm_stm32_init, NULL, \
|
2020-12-09 22:38:54 +01:00
|
|
|
|
&pwm_stm32_data_##index, \
|
2020-04-21 21:50:03 +02:00
|
|
|
|
&pwm_stm32_config_##index, POST_KERNEL, \
|
2022-09-21 11:22:06 +02:00
|
|
|
|
CONFIG_PWM_INIT_PRIORITY, \
|
2020-04-21 21:50:03 +02:00
|
|
|
|
&pwm_stm32_driver_api);
|
|
|
|
|
|
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT)
|