drivers: stm32: Convert STM32 drivers to new DT_INST macros
Convert older DT_INST_ macro use in STM32 drivers to the new include/devicetree.h DT_INST macro APIs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
parent
f9efa0ce67
commit
989484b4bf
13 changed files with 218 additions and 192 deletions
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@ -6,6 +6,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_adc
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#include <errno.h>
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#include <drivers/adc.h>
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@ -652,11 +654,11 @@ static const struct adc_driver_api api_stm32_driver_api = {
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static void adc_stm32_cfg_func_##index(void); \
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\
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static const struct adc_stm32_cfg adc_stm32_cfg_##index = { \
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.base = (ADC_TypeDef *)DT_INST_##index##_ST_STM32_ADC_BASE_ADDRESS,\
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.base = (ADC_TypeDef *)DT_INST_REG_ADDR(index),\
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.irq_cfg_func = adc_stm32_cfg_func_##index, \
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.pclken = { \
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.enr = DT_INST_##index##_ST_STM32_ADC_CLOCK_BITS, \
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.bus = DT_INST_##index##_ST_STM32_ADC_CLOCK_BUS, \
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.enr = DT_INST_CLOCKS_CELL(index, bits), \
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.bus = DT_INST_CLOCKS_CELL(index, bus), \
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}, \
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}; \
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static struct adc_stm32_data adc_stm32_data_##index = { \
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@ -665,7 +667,7 @@ static struct adc_stm32_data adc_stm32_data_##index = { \
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ADC_CONTEXT_INIT_SYNC(adc_stm32_data_##index, ctx), \
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}; \
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\
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DEVICE_AND_API_INIT(adc_##index, DT_INST_##index##_ST_STM32_ADC_LABEL, \
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DEVICE_AND_API_INIT(adc_##index, DT_INST_LABEL(index), \
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&adc_stm32_init, \
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&adc_stm32_data_##index, &adc_stm32_cfg_##index, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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@ -673,12 +675,12 @@ DEVICE_AND_API_INIT(adc_##index, DT_INST_##index##_ST_STM32_ADC_LABEL, \
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\
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static void adc_stm32_cfg_func_##index(void) \
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{ \
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IRQ_CONNECT(DT_INST_##index##_ST_STM32_ADC_IRQ_0, \
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DT_INST_##index##_ST_STM32_ADC_IRQ_0_PRIORITY, \
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IRQ_CONNECT(DT_INST_IRQN(index), \
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DT_INST_IRQ(index, priority), \
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adc_stm32_isr, DEVICE_GET(adc_##index), 0); \
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irq_enable(DT_INST_##index##_ST_STM32_ADC_IRQ_0); \
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irq_enable(DT_INST_IRQN(index)); \
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}
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#ifdef DT_INST_0_ST_STM32_ADC
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#if DT_HAS_DRV_INST(0)
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STM32_ADC_INIT(0);
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#endif /* DT_INST_0_ST_STM32_ADC */
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#endif /* DT_HAS_DRV_INST(0) */
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@ -9,6 +9,8 @@
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*
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*/
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#define DT_DRV_COMPAT st_stm32_rtc
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#include <time.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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@ -348,8 +350,8 @@ static const struct rtc_stm32_config rtc_config = {
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.channels = 1,
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},
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.pclken = {
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.enr = DT_INST_0_ST_STM32_RTC_CLOCK_BITS,
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.bus = DT_INST_0_ST_STM32_RTC_CLOCK_BUS,
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.enr = DT_INST_CLOCKS_CELL(0, bits),
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.bus = DT_INST_CLOCKS_CELL(0, bus),
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},
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.ll_rtc_config = {
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.HourFormat = LL_RTC_HOURFORMAT_24HOUR,
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@ -378,14 +380,14 @@ static const struct counter_driver_api rtc_stm32_driver_api = {
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.get_max_relative_alarm = rtc_stm32_get_max_relative_alarm,
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};
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DEVICE_AND_API_INIT(rtc_stm32, DT_INST_0_ST_STM32_RTC_LABEL, &rtc_stm32_init,
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DEVICE_AND_API_INIT(rtc_stm32, DT_INST_LABEL(0), &rtc_stm32_init,
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&rtc_data, &rtc_config, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &rtc_stm32_driver_api);
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static void rtc_stm32_irq_config(struct device *dev)
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{
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IRQ_CONNECT(DT_INST_0_ST_STM32_RTC_IRQ_0,
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DT_INST_0_ST_STM32_RTC_IRQ_0_PRIORITY,
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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rtc_stm32_isr, DEVICE_GET(rtc_stm32), 0);
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irq_enable(DT_INST_0_ST_STM32_RTC_IRQ_0);
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irq_enable(DT_INST_IRQN(0));
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}
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_cryp
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#include <init.h>
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#include <kernel.h>
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#include <device.h>
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@ -455,12 +457,12 @@ static struct crypto_stm32_data crypto_stm32_dev_data = {
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static struct crypto_stm32_config crypto_stm32_dev_config = {
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.pclken = {
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.enr = DT_INST_0_ST_STM32_CRYP_CLOCK_BITS,
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.bus = DT_INST_0_ST_STM32_CRYP_CLOCK_BUS
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.enr = DT_INST_CLOCKS_CELL(0, bits),
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.bus = DT_INST_CLOCKS_CELL(0, bus)
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}
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};
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DEVICE_AND_API_INIT(crypto_stm32, DT_INST_0_ST_STM32_CRYP_LABEL,
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DEVICE_AND_API_INIT(crypto_stm32, DT_INST_LABEL(0),
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crypto_stm32_init, &crypto_stm32_dev_data,
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&crypto_stm32_dev_config, POST_KERNEL,
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CONFIG_CRYPTO_INIT_PRIORITY, (void *)&crypto_enc_funcs);
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@ -5,6 +5,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_dma
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/**
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* @brief Common part of DMA drivers for stm32.
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* @note Functions named with stm32_dma_* are SoCs related functions
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@ -523,11 +525,11 @@ static const struct dma_driver_api dma_funcs = {
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static void dma_stm32_config_irq_##index(struct device *dev); \
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\
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const struct dma_stm32_config dma_stm32_config_##index = { \
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.pclken = { .bus = DT_INST_##index##_ST_STM32_DMA_CLOCK_BUS, \
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.enr = DT_INST_##index##_ST_STM32_DMA_CLOCK_BITS }, \
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.pclken = { .bus = DT_INST_CLOCKS_CELL(index, bus), \
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.enr = DT_INST_CLOCKS_CELL(index, bits) }, \
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.config_irq = dma_stm32_config_irq_##index, \
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.base = DT_INST_##index##_ST_STM32_DMA_BASE_ADDRESS, \
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.support_m2m = DT_INST_##index##_ST_STM32_DMA_ST_MEM2MEM, \
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.base = DT_INST_REG_ADDR(index), \
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.support_m2m = DT_INST_PROP(index, st_mem2mem), \
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}; \
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\
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static struct dma_stm32_data dma_stm32_data_##index = { \
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@ -535,7 +537,7 @@ static struct dma_stm32_data dma_stm32_data_##index = { \
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.streams = NULL, \
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}; \
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\
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DEVICE_AND_API_INIT(dma_##index, DT_INST_##index##_ST_STM32_DMA_LABEL, \
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DEVICE_AND_API_INIT(dma_##index, DT_INST_LABEL(index), \
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&dma_stm32_init, \
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&dma_stm32_data_##index, &dma_stm32_config_##index, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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@ -549,16 +551,16 @@ static void dma_stm32_irq_##chan(void *arg) \
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#define IRQ_INIT(dma, chan) \
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do { \
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if (!irq_is_enabled(DT_INST_##dma##_ST_STM32_DMA_IRQ_##chan)) { \
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irq_connect_dynamic(DT_INST_##dma##_ST_STM32_DMA_IRQ_##chan,\
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DT_INST_##dma##_ST_STM32_DMA_IRQ_##chan##_PRIORITY,\
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if (!irq_is_enabled(DT_INST_IRQ_BY_IDX(dma, chan, irq))) { \
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irq_connect_dynamic(DT_INST_IRQ_BY_IDX(dma, chan, irq), \
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DT_INST_IRQ_BY_IDX(dma, chan, priority), \
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dma_stm32_irq_handler, dev, 0); \
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irq_enable(DT_INST_##dma##_ST_STM32_DMA_IRQ_##chan); \
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irq_enable(DT_INST_IRQ_BY_IDX(dma, chan, irq)); \
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} \
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data->max_streams++; \
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} while (0)
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#ifdef DT_INST_0_ST_STM32_DMA
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#if DT_HAS_DRV_INST(0)
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DMA_INIT(0);
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static void dma_stm32_config_irq_0(struct device *dev)
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@ -570,21 +572,21 @@ static void dma_stm32_config_irq_0(struct device *dev)
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IRQ_INIT(0, 2);
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IRQ_INIT(0, 3);
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IRQ_INIT(0, 4);
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#ifdef DT_INST_0_ST_STM32_DMA_IRQ_5
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#if DT_INST_IRQ_HAS_IDX(0, 5)
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IRQ_INIT(0, 5);
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#ifdef DT_INST_0_ST_STM32_DMA_IRQ_6
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#if DT_INST_IRQ_HAS_IDX(0, 6)
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IRQ_INIT(0, 6);
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#ifdef DT_INST_0_ST_STM32_DMA_IRQ_7
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#if DT_INST_IRQ_HAS_IDX(0, 7)
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IRQ_INIT(0, 7);
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#endif /* DT_INST_0_ST_STM32_DMA_IRQ_5 */
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#endif /* DT_INST_0_ST_STM32_DMA_IRQ_6 */
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#endif /* DT_INST_0_ST_STM32_DMA_IRQ_7 */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 5) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 6) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 7) */
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/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
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}
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#endif /* DT_INST_0_ST_STM32_DMA */
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#endif /* DT_HAS_DRV_INST(0) */
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#ifdef DT_INST_1_ST_STM32_DMA
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#if DT_HAS_DRV_INST(1)
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DMA_INIT(1);
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static void dma_stm32_config_irq_1(struct device *dev)
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@ -596,15 +598,15 @@ static void dma_stm32_config_irq_1(struct device *dev)
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IRQ_INIT(1, 2);
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IRQ_INIT(1, 3);
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IRQ_INIT(1, 4);
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#ifdef DT_INST_1_ST_STM32_DMA_IRQ_5
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#if DT_INST_IRQ_HAS_IDX(1, 5)
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IRQ_INIT(1, 5);
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#ifdef DT_INST_1_ST_STM32_DMA_IRQ_6
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#if DT_INST_IRQ_HAS_IDX(1, 6)
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IRQ_INIT(1, 6);
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#ifdef DT_INST_1_ST_STM32_DMA_IRQ_7
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#if DT_INST_IRQ_HAS_IDX(1, 7)
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IRQ_INIT(1, 7);
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#endif /* DT_INST_1_ST_STM32_DMA_IRQ_5 */
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#endif /* DT_INST_1_ST_STM32_DMA_IRQ_6 */
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#endif /* DT_INST_1_ST_STM32_DMA_IRQ_7 */
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#endif /* DT_INST_IRQ_HAS_IDX(1, 5) */
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#endif /* DT_INST_IRQ_HAS_IDX(1, 6) */
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#endif /* DT_INST_IRQ_HAS_IDX(1, 7) */
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/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
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}
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#endif /* DT_INST_1_ST_STM32_DMA */
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#endif /* DT_HAS_DRV_INST(1) */
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_eeprom
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#include <drivers/eeprom.h>
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#include <soc.h>
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@ -115,11 +117,11 @@ static const struct eeprom_driver_api eeprom_stm32_api = {
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};
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static const struct eeprom_stm32_config eeprom_config = {
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.addr = DT_INST_0_ST_STM32_EEPROM_BASE_ADDRESS,
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.size = DT_INST_0_ST_STM32_EEPROM_SIZE,
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.addr = DT_INST_REG_ADDR(0),
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.size = DT_INST_REG_SIZE(0),
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};
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DEVICE_AND_API_INIT(eeprom_stm32, DT_INST_0_ST_STM32_EEPROM_LABEL,
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DEVICE_AND_API_INIT(eeprom_stm32, DT_INST_LABEL(0),
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&eeprom_stm32_init, NULL,
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&eeprom_config, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &eeprom_stm32_api);
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@ -6,6 +6,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT soc_nv_flash
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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@ -279,7 +281,7 @@ static int flash_stm32_write_protection(struct device *dev, bool enable)
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}
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static struct flash_stm32_priv flash_data = {
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.regs = (FLASH_TypeDef *) DT_INST_0_SOC_NV_FLASH_BASE_ADDRESS,
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.regs = (FLASH_TypeDef *) DT_INST_REG_ADDR(0),
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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@ -299,8 +301,8 @@ static const struct flash_driver_api flash_stm32_api = {
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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.page_layout = flash_stm32_page_layout,
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#endif
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#ifdef DT_INST_0_SOC_NV_FLASH_WRITE_BLOCK_SIZE
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.write_block_size = DT_INST_0_SOC_NV_FLASH_WRITE_BLOCK_SIZE,
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#if DT_INST_NODE_HAS_PROP(0, write_block_size)
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.write_block_size = DT_INST_PROP(0, write_block_size),
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#else
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#error Flash write block size not available
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/* Flash Write block size is extracted from device tree */
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_ipcc_mailbox
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#include <drivers/clock_control.h>
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#include <device.h>
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#include <errno.h>
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@ -285,14 +287,14 @@ static void stm32_ipcc_mailbox_config_func(struct device *dev);
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/* Config MAILBOX 0 */
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static const struct stm32_ipcc_mailbox_config stm32_ipcc_mailbox_0_config = {
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.irq_config_func = stm32_ipcc_mailbox_config_func,
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.ipcc = (IPCC_TypeDef *)DT_INST_0_ST_STM32_IPCC_MAILBOX_BASE_ADDRESS,
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.pclken = { .bus = DT_INST_0_ST_STM32_IPCC_MAILBOX_CLOCK_BUS,
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.enr = DT_INST_0_ST_STM32_IPCC_MAILBOX_CLOCK_BITS
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.ipcc = (IPCC_TypeDef *)DT_INST_REG_ADDR(0),
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.pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
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.enr = DT_INST_CLOCKS_CELL(0, bits)
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},
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};
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DEVICE_AND_API_INIT(mailbox_0, DT_INST_0_ST_STM32_IPCC_MAILBOX_LABEL,
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DEVICE_AND_API_INIT(mailbox_0, DT_INST_LABEL(0),
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&stm32_ipcc_mailbox_init,
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&stm32_IPCC_data, &stm32_ipcc_mailbox_0_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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@ -300,14 +302,14 @@ DEVICE_AND_API_INIT(mailbox_0, DT_INST_0_ST_STM32_IPCC_MAILBOX_LABEL,
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static void stm32_ipcc_mailbox_config_func(struct device *dev)
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{
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IRQ_CONNECT(DT_INST_0_ST_STM32_IPCC_MAILBOX_IRQ_RXO,
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DT_INST_0_ST_STM32_IPCC_MAILBOX_IRQ_RXO_PRIORITY,
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, rxo, irq),
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DT_INST_IRQ_BY_NAME(0, rxo, priority),
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stm32_ipcc_mailbox_rx_isr, DEVICE_GET(mailbox_0), 0);
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IRQ_CONNECT(DT_INST_0_ST_STM32_IPCC_MAILBOX_IRQ_TXF,
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DT_INST_0_ST_STM32_IPCC_MAILBOX_IRQ_TXF_PRIORITY,
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, txf, irq),
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DT_INST_IRQ_BY_NAME(0, txf, priority),
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stm32_ipcc_mailbox_tx_isr, DEVICE_GET(mailbox_0), 0);
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irq_enable(DT_INST_0_ST_STM32_IPCC_MAILBOX_IRQ_RXO);
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irq_enable(DT_INST_0_ST_STM32_IPCC_MAILBOX_IRQ_TXF);
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irq_enable(DT_INST_IRQ_BY_NAME(0, rxo, irq));
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irq_enable(DT_INST_IRQ_BY_NAME(0, txf, irq));
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}
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_pwm
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#include <errno.h>
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#include <soc.h>
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@ -219,101 +221,101 @@ static int pwm_stm32_init(struct device *dev)
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#define PWM_DEVICE_INIT_STM32(index) \
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static struct pwm_stm32_data pwm_stm32_dev_data_##index = { \
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/* Default case */ \
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.pwm_prescaler = DT_INST_##index##_ST_STM32_PWM_ST_PRESCALER,\
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.pwm_prescaler = DT_INST_PROP(index, st_prescaler),\
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}; \
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\
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static const struct pwm_stm32_config pwm_stm32_dev_cfg_##index = {\
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.pwm_base = DT_INST_##index##_ST_STM32_TIMERS_BASE_ADDRESS,\
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.pwm_base = DT_REG_ADDR(DT_INST(index, st_stm32_timers)),\
|
||||
.pclken = { \
|
||||
.bus = DT_INST_##index##_ST_STM32_TIMERS_CLOCK_BUS,\
|
||||
.enr = DT_INST_##index##_ST_STM32_TIMERS_CLOCK_BITS\
|
||||
.bus = DT_CLOCKS_CELL(DT_INST(index, st_stm32_timers), bus),\
|
||||
.enr = DT_CLOCKS_CELL(DT_INST(index, st_stm32_timers), bits)\
|
||||
},\
|
||||
}; \
|
||||
\
|
||||
DEVICE_AND_API_INIT(pwm_stm32_##index, \
|
||||
DT_INST_##index##_ST_STM32_PWM_LABEL, \
|
||||
DT_INST_LABEL(index), \
|
||||
pwm_stm32_init, \
|
||||
&pwm_stm32_dev_data_##index, \
|
||||
&pwm_stm32_dev_cfg_##index, \
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,\
|
||||
&pwm_stm32_drv_api_funcs)
|
||||
|
||||
#ifdef DT_INST_0_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(0)
|
||||
PWM_DEVICE_INIT_STM32(0);
|
||||
#endif /* DT_INST_0_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(0) */
|
||||
|
||||
#ifdef DT_INST_1_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(1)
|
||||
PWM_DEVICE_INIT_STM32(1);
|
||||
#endif /* DT_INST_1_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(1) */
|
||||
|
||||
#ifdef DT_INST_2_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(2)
|
||||
PWM_DEVICE_INIT_STM32(2);
|
||||
#endif /* DT_INST_2_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(2) */
|
||||
|
||||
#ifdef DT_INST_3_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(3)
|
||||
PWM_DEVICE_INIT_STM32(3);
|
||||
#endif /* DT_INST_3_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(3) */
|
||||
|
||||
#ifdef DT_INST_4_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(4)
|
||||
PWM_DEVICE_INIT_STM32(4);
|
||||
#endif /* DT_INST_4_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(4) */
|
||||
|
||||
#ifdef DT_INST_5_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(5)
|
||||
PWM_DEVICE_INIT_STM32(5);
|
||||
#endif /* DT_INST_5_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(5) */
|
||||
|
||||
#ifdef DT_INST_6_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(6)
|
||||
PWM_DEVICE_INIT_STM32(6);
|
||||
#endif /* DT_INST_6_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(6) */
|
||||
|
||||
#ifdef DT_INST_7_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(7)
|
||||
PWM_DEVICE_INIT_STM32(7);
|
||||
#endif /* DT_INST_7_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(7) */
|
||||
|
||||
#ifdef DT_INST_8_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(8)
|
||||
PWM_DEVICE_INIT_STM32(8);
|
||||
#endif /* DT_INST_8_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(8) */
|
||||
|
||||
#ifdef DT_INST_9_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(9)
|
||||
PWM_DEVICE_INIT_STM32(9);
|
||||
#endif /* DT_INST_9_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(9) */
|
||||
|
||||
#ifdef DT_INST_10_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(10)
|
||||
PWM_DEVICE_INIT_STM32(10);
|
||||
#endif /* DT_INST_10_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(10) */
|
||||
|
||||
#ifdef DT_INST_11_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(11)
|
||||
PWM_DEVICE_INIT_STM32(11);
|
||||
#endif /* DT_INST_11_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(11) */
|
||||
|
||||
#ifdef DT_INST_12_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(12)
|
||||
PWM_DEVICE_INIT_STM32(12);
|
||||
#endif /* DT_INST_12_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(12) */
|
||||
|
||||
#ifdef DT_INST_13_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(13)
|
||||
PWM_DEVICE_INIT_STM32(13);
|
||||
#endif /* DT_INST_13_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(13) */
|
||||
|
||||
#ifdef DT_INST_14_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(14)
|
||||
PWM_DEVICE_INIT_STM32(14);
|
||||
#endif /* DT_INST_14_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(14) */
|
||||
|
||||
#ifdef DT_INST_15_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(15)
|
||||
PWM_DEVICE_INIT_STM32(15);
|
||||
#endif /* DT_INST_15_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(15) */
|
||||
|
||||
#ifdef DT_INST_16_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(16)
|
||||
PWM_DEVICE_INIT_STM32(16);
|
||||
#endif /* DT_INST_16_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(16) */
|
||||
|
||||
#ifdef DT_INST_17_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(17)
|
||||
PWM_DEVICE_INIT_STM32(17);
|
||||
#endif /* DT_INST_17_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(17) */
|
||||
|
||||
#ifdef DT_INST_18_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(18)
|
||||
PWM_DEVICE_INIT_STM32(18);
|
||||
#endif /* DT_INST_18_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(18) */
|
||||
|
||||
#ifdef DT_INST_19_ST_STM32_PWM
|
||||
#if DT_HAS_DRV_INST(19)
|
||||
PWM_DEVICE_INIT_STM32(19);
|
||||
#endif /* DT_INST_19_ST_STM32_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(19) */
|
||||
|
|
|
@ -5,6 +5,8 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT st_stm32_uart
|
||||
|
||||
/**
|
||||
* @brief Driver for UART port on STM32 family processor.
|
||||
* @note LPUART and U(S)ART have the same base and
|
||||
|
@ -711,11 +713,11 @@ static int uart_stm32_init(struct device *dev)
|
|||
#define STM32_UART_IRQ_HANDLER(index) \
|
||||
static void uart_stm32_irq_config_func_##index(struct device *dev) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_INST_##index##_ST_STM32_UART_IRQ_0, \
|
||||
DT_INST_##index##_ST_STM32_UART_IRQ_0_PRIORITY, \
|
||||
IRQ_CONNECT(DT_INST_IRQN(index), \
|
||||
DT_INST_IRQ(index, priority), \
|
||||
uart_stm32_isr, DEVICE_GET(uart_stm32_##index), \
|
||||
0); \
|
||||
irq_enable(DT_INST_##index##_ST_STM32_UART_IRQ_0); \
|
||||
irq_enable(DT_INST_IRQN(index)); \
|
||||
}
|
||||
#else
|
||||
#define STM32_UART_IRQ_HANDLER_DECL(index)
|
||||
|
@ -728,20 +730,20 @@ STM32_UART_IRQ_HANDLER_DECL(index); \
|
|||
\
|
||||
static const struct uart_stm32_config uart_stm32_cfg_##index = { \
|
||||
.uconf = { \
|
||||
.base = (u8_t *)DT_INST_##index##_ST_STM32_UART_BASE_ADDRESS,\
|
||||
.base = (u8_t *)DT_INST_REG_ADDR(index),\
|
||||
STM32_UART_IRQ_HANDLER_FUNC(index) \
|
||||
}, \
|
||||
.pclken = { .bus = DT_INST_##index##_ST_STM32_UART_CLOCK_BUS, \
|
||||
.enr = DT_INST_##index##_ST_STM32_UART_CLOCK_BITS \
|
||||
.pclken = { .bus = DT_INST_CLOCKS_CELL(index, bus), \
|
||||
.enr = DT_INST_CLOCKS_CELL(index, bits) \
|
||||
}, \
|
||||
.hw_flow_control = DT_INST_##index##_ST_STM32_UART_HW_FLOW_CONTROL\
|
||||
.hw_flow_control = DT_INST_PROP(index, hw_flow_control)\
|
||||
}; \
|
||||
\
|
||||
static struct uart_stm32_data uart_stm32_data_##index = { \
|
||||
.baud_rate = DT_INST_##index##_ST_STM32_UART_CURRENT_SPEED \
|
||||
.baud_rate = DT_INST_PROP(index, current_speed) \
|
||||
}; \
|
||||
\
|
||||
DEVICE_AND_API_INIT(uart_stm32_##index, DT_INST_##index##_ST_STM32_UART_LABEL,\
|
||||
DEVICE_AND_API_INIT(uart_stm32_##index, DT_INST_LABEL(index),\
|
||||
&uart_stm32_init, \
|
||||
&uart_stm32_data_##index, &uart_stm32_cfg_##index, \
|
||||
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
||||
|
@ -749,46 +751,46 @@ DEVICE_AND_API_INIT(uart_stm32_##index, DT_INST_##index##_ST_STM32_UART_LABEL,\
|
|||
\
|
||||
STM32_UART_IRQ_HANDLER(index)
|
||||
|
||||
#ifdef DT_INST_0_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(0)
|
||||
STM32_UART_INIT(0)
|
||||
#endif /* DT_INST_0_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(0) */
|
||||
|
||||
#ifdef DT_INST_1_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(1)
|
||||
STM32_UART_INIT(1)
|
||||
#endif /* DT_INST_1_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(1) */
|
||||
|
||||
#ifdef DT_INST_2_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(2)
|
||||
STM32_UART_INIT(2)
|
||||
#endif /* DT_INST_2_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(2) */
|
||||
|
||||
#ifdef DT_INST_3_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(3)
|
||||
STM32_UART_INIT(3)
|
||||
#endif /* DT_INST_3_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(3) */
|
||||
|
||||
#ifdef DT_INST_4_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(4)
|
||||
STM32_UART_INIT(4)
|
||||
#endif /* DT_INST_4_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(4) */
|
||||
|
||||
#ifdef DT_INST_5_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(5)
|
||||
STM32_UART_INIT(5)
|
||||
#endif /* DT_INST_5_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(5) */
|
||||
|
||||
#ifdef DT_INST_6_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(6)
|
||||
STM32_UART_INIT(6)
|
||||
#endif /* DT_INST_6_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(6) */
|
||||
|
||||
#ifdef DT_INST_7_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(7)
|
||||
STM32_UART_INIT(7)
|
||||
#endif /* DT_INST_7_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(7) */
|
||||
|
||||
#ifdef DT_INST_8_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(8)
|
||||
STM32_UART_INIT(8)
|
||||
#endif /* DT_INST_8_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(8) */
|
||||
|
||||
#ifdef DT_INST_9_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(9)
|
||||
STM32_UART_INIT(9)
|
||||
#endif /* DT_INST_9_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(9) */
|
||||
|
||||
#ifdef DT_INST_10_ST_STM32_UART
|
||||
#if DT_HAS_DRV_INST(10)
|
||||
STM32_UART_INIT(10)
|
||||
#endif /* DT_INST_10_ST_STM32_UART */
|
||||
#endif /* DT_HAS_DRV_INST(10) */
|
||||
|
|
|
@ -4,6 +4,8 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT st_stm32_spi
|
||||
|
||||
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
|
||||
#include <logging/log.h>
|
||||
LOG_MODULE_REGISTER(spi_ll_stm32);
|
||||
|
@ -506,10 +508,10 @@ static int spi_stm32_init(struct device *dev)
|
|||
#define STM32_SPI_IRQ_HANDLER(id) \
|
||||
static void spi_stm32_irq_config_func_##id(struct device *dev) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_INST_##id##_ST_STM32_SPI_IRQ_0, \
|
||||
DT_INST_##id##_ST_STM32_SPI_IRQ_0_PRIORITY, \
|
||||
IRQ_CONNECT(DT_INST_IRQN(id), \
|
||||
DT_INST_IRQ(id, priority), \
|
||||
spi_stm32_isr, DEVICE_GET(spi_stm32_##id), 0); \
|
||||
irq_enable(DT_INST_##id##_ST_STM32_SPI_IRQ_0); \
|
||||
irq_enable(DT_INST_IRQN(id)); \
|
||||
}
|
||||
#else
|
||||
#define STM32_SPI_IRQ_HANDLER_DECL(id)
|
||||
|
@ -521,10 +523,10 @@ static void spi_stm32_irq_config_func_##id(struct device *dev) \
|
|||
STM32_SPI_IRQ_HANDLER_DECL(id); \
|
||||
\
|
||||
static const struct spi_stm32_config spi_stm32_cfg_##id = { \
|
||||
.spi = (SPI_TypeDef *) DT_INST_##id##_ST_STM32_SPI_BASE_ADDRESS,\
|
||||
.spi = (SPI_TypeDef *) DT_INST_REG_ADDR(id),\
|
||||
.pclken = { \
|
||||
.enr = DT_INST_##id##_ST_STM32_SPI_CLOCK_BITS, \
|
||||
.bus = DT_INST_##id##_ST_STM32_SPI_CLOCK_BUS \
|
||||
.enr = DT_INST_CLOCKS_CELL(id, bits), \
|
||||
.bus = DT_INST_CLOCKS_CELL(id, bus) \
|
||||
}, \
|
||||
STM32_SPI_IRQ_HANDLER_FUNC(id) \
|
||||
}; \
|
||||
|
@ -534,7 +536,7 @@ static struct spi_stm32_data spi_stm32_dev_data_##id = { \
|
|||
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_##id, ctx), \
|
||||
}; \
|
||||
\
|
||||
DEVICE_AND_API_INIT(spi_stm32_##id, DT_INST_##id##_ST_STM32_SPI_LABEL, \
|
||||
DEVICE_AND_API_INIT(spi_stm32_##id, DT_INST_LABEL(id), \
|
||||
&spi_stm32_init, \
|
||||
&spi_stm32_dev_data_##id, &spi_stm32_cfg_##id, \
|
||||
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
|
||||
|
@ -542,26 +544,26 @@ DEVICE_AND_API_INIT(spi_stm32_##id, DT_INST_##id##_ST_STM32_SPI_LABEL, \
|
|||
\
|
||||
STM32_SPI_IRQ_HANDLER(id)
|
||||
|
||||
#ifdef DT_INST_0_ST_STM32_SPI
|
||||
#if DT_HAS_DRV_INST(0)
|
||||
STM32_SPI_INIT(0)
|
||||
#endif /* DT_INST_0_ST_STM32_SPI */
|
||||
#endif /* DT_HAS_DRV_INST(0) */
|
||||
|
||||
#ifdef DT_INST_1_ST_STM32_SPI
|
||||
#if DT_HAS_DRV_INST(1)
|
||||
STM32_SPI_INIT(1)
|
||||
#endif /* DT_INST_1_ST_STM32_SPI */
|
||||
#endif /* DT_HAS_DRV_INST(1) */
|
||||
|
||||
#ifdef DT_INST_2_ST_STM32_SPI
|
||||
#if DT_HAS_DRV_INST(2)
|
||||
STM32_SPI_INIT(2)
|
||||
#endif /* DT_INST_2_ST_STM32_SPI */
|
||||
#endif /* DT_HAS_DRV_INST(2) */
|
||||
|
||||
#ifdef DT_INST_3_ST_STM32_SPI
|
||||
#if DT_HAS_DRV_INST(3)
|
||||
STM32_SPI_INIT(3)
|
||||
#endif /* DT_INST_3_ST_STM32_SPI */
|
||||
#endif /* DT_HAS_DRV_INST(3) */
|
||||
|
||||
#ifdef DT_INST_4_ST_STM32_SPI
|
||||
#if DT_HAS_DRV_INST(4)
|
||||
STM32_SPI_INIT(4)
|
||||
#endif /* DT_INST_4_ST_STM32_SPI */
|
||||
#endif /* DT_HAS_DRV_INST(4) */
|
||||
|
||||
#ifdef DT_INST_5_ST_STM32_SPI
|
||||
#if DT_HAS_DRV_INST(5)
|
||||
STM32_SPI_INIT(5)
|
||||
#endif /* DT_INST_5_ST_STM32_SPI */
|
||||
#endif /* DT_HAS_DRV_INST(5) */
|
||||
|
|
|
@ -1,5 +1,7 @@
|
|||
/* USB device controller driver for STM32 devices */
|
||||
|
||||
#define DT_DRV_COMPAT st_stm32_usb
|
||||
|
||||
/*
|
||||
* Copyright (c) 2017 Christer Weinigel.
|
||||
* Copyright (c) 2017, I-SENSE group of ICCS
|
||||
|
@ -60,34 +62,34 @@ LOG_MODULE_REGISTER(usb_dc_stm32);
|
|||
#endif
|
||||
|
||||
#if defined(DT_COMPAT_ST_STM32_OTGHS)
|
||||
#define DT_USB_BASE_ADDRESS DT_INST_0_ST_STM32_OTGHS_BASE_ADDRESS
|
||||
#define DT_USB_IRQ DT_INST_0_ST_STM32_OTGHS_IRQ_OTGHS
|
||||
#define DT_USB_IRQ_PRI DT_INST_0_ST_STM32_OTGHS_IRQ_OTGHS_PRIORITY
|
||||
#define DT_USB_NUM_BIDIR_ENDPOINTS DT_INST_0_ST_STM32_OTGHS_NUM_BIDIR_ENDPOINTS
|
||||
#define DT_USB_RAM_SIZE DT_INST_0_ST_STM32_OTGHS_RAM_SIZE
|
||||
#define DT_USB_MAXIMUM_SPEED DT_INST_0_ST_STM32_OTGHS_MAXIMUM_SPEED
|
||||
#define DT_USB_CLOCK_BITS DT_INST_0_ST_STM32_OTGHS_CLOCK_BITS
|
||||
#define DT_USB_CLOCK_BUS DT_INST_0_ST_STM32_OTGHS_CLOCK_BUS
|
||||
#define DT_USB_BASE_ADDRESS DT_REG_ADDR(DT_INST(0, st_stm32_otghs))
|
||||
#define DT_USB_IRQ DT_IRQ_BY_NAME(DT_INST(0, st_stm32_otghs), otghs, irq)
|
||||
#define DT_USB_IRQ_PRI DT_IRQ_BY_NAME(DT_INST(0, st_stm32_otghs), otghs, priority)
|
||||
#define DT_USB_NUM_BIDIR_ENDPOINTS DT_PROP(DT_INST(0, st_stm32_otghs), num_bidir_endpoints)
|
||||
#define DT_USB_RAM_SIZE DT_PROP(DT_INST(0, st_stm32_otghs), ram_size)
|
||||
#define DT_USB_MAXIMUM_SPEED DT_PROP(DT_INST(0, st_stm32_otghs), maximum_speed)
|
||||
#define DT_USB_CLOCK_BITS DT_CLOCKS_CELL(DT_INST(0, st_stm32_otghs), bits)
|
||||
#define DT_USB_CLOCK_BUS DT_CLOCKS_CELL(DT_INST(0, st_stm32_otghs), bus)
|
||||
#elif defined(DT_COMPAT_ST_STM32_OTGFS)
|
||||
#define DT_USB_BASE_ADDRESS DT_INST_0_ST_STM32_OTGFS_BASE_ADDRESS
|
||||
#define DT_USB_IRQ DT_INST_0_ST_STM32_OTGFS_IRQ_OTGFS
|
||||
#define DT_USB_IRQ_PRI DT_INST_0_ST_STM32_OTGFS_IRQ_OTGFS_PRIORITY
|
||||
#define DT_USB_NUM_BIDIR_ENDPOINTS DT_INST_0_ST_STM32_OTGFS_NUM_BIDIR_ENDPOINTS
|
||||
#define DT_USB_RAM_SIZE DT_INST_0_ST_STM32_OTGFS_RAM_SIZE
|
||||
#define DT_USB_MAXIMUM_SPEED DT_INST_0_ST_STM32_OTGFS_MAXIMUM_SPEED
|
||||
#define DT_USB_CLOCK_BITS DT_INST_0_ST_STM32_OTGFS_CLOCK_BITS
|
||||
#define DT_USB_CLOCK_BUS DT_INST_0_ST_STM32_OTGFS_CLOCK_BUS
|
||||
#define DT_USB_BASE_ADDRESS DT_REG_ADDR(DT_INST(0, st_stm32_otgfs))
|
||||
#define DT_USB_IRQ DT_IRQ_BY_NAME(DT_INST(0, st_stm32_otgfs), otgfs, irq)
|
||||
#define DT_USB_IRQ_PRI DT_IRQ_BY_NAME(DT_INST(0, st_stm32_otgfs), otgfs, priority)
|
||||
#define DT_USB_NUM_BIDIR_ENDPOINTS DT_PROP(DT_INST(0, st_stm32_otgfs), num_bidir_endpoints)
|
||||
#define DT_USB_RAM_SIZE DT_PROP(DT_INST(0, st_stm32_otgfs), ram_size)
|
||||
#define DT_USB_MAXIMUM_SPEED DT_PROP(DT_INST(0, st_stm32_otgfs), maximum_speed)
|
||||
#define DT_USB_CLOCK_BITS DT_CLOCKS_CELL(DT_INST(0, st_stm32_otgfs), bits)
|
||||
#define DT_USB_CLOCK_BUS DT_CLOCKS_CELL(DT_INST(0, st_stm32_otgfs), bus)
|
||||
#elif defined(DT_COMPAT_ST_STM32_USB)
|
||||
#define DT_USB_BASE_ADDRESS DT_INST_0_ST_STM32_USB_BASE_ADDRESS
|
||||
#define DT_USB_IRQ DT_INST_0_ST_STM32_USB_IRQ_USB
|
||||
#define DT_USB_IRQ_PRI DT_INST_0_ST_STM32_USB_IRQ_USB_PRIORITY
|
||||
#define DT_USB_NUM_BIDIR_ENDPOINTS DT_INST_0_ST_STM32_USB_NUM_BIDIR_ENDPOINTS
|
||||
#define DT_USB_RAM_SIZE DT_INST_0_ST_STM32_USB_RAM_SIZE
|
||||
#define DT_USB_MAXIMUM_SPEED DT_INST_0_ST_STM32_USB_MAXIMUM_SPEED
|
||||
#define DT_USB_CLOCK_BITS DT_INST_0_ST_STM32_USB_CLOCK_BITS
|
||||
#define DT_USB_CLOCK_BUS DT_INST_0_ST_STM32_USB_CLOCK_BUS
|
||||
#ifdef DT_INST_0_ST_STM32_USB_ENABLE_PIN_REMAP
|
||||
#define DT_USB_ENABLE_PIN_REMAP DT_INST_0_ST_STM32_USB_ENABLE_PIN_REMAP
|
||||
#define DT_USB_BASE_ADDRESS DT_REG_ADDR(DT_INST(0, st_stm32_usb))
|
||||
#define DT_USB_IRQ DT_IRQ_BY_NAME(DT_INST(0, st_stm32_usb), usb, irq)
|
||||
#define DT_USB_IRQ_PRI DT_IRQ_BY_NAME(DT_INST(0, st_stm32_usb), usb, priority)
|
||||
#define DT_USB_NUM_BIDIR_ENDPOINTS DT_PROP(DT_INST(0, st_stm32_usb), num_bidir_endpoints)
|
||||
#define DT_USB_RAM_SIZE DT_PROP(DT_INST(0, st_stm32_usb), ram_size)
|
||||
#define DT_USB_MAXIMUM_SPEED DT_PROP(DT_INST(0, st_stm32_usb), maximum_speed)
|
||||
#define DT_USB_CLOCK_BITS DT_CLOCKS_CELL(DT_INST(0, st_stm32_usb), bits)
|
||||
#define DT_USB_CLOCK_BUS DT_CLOCKS_CELL(DT_INST(0, st_stm32_usb), bus)
|
||||
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_usb), enable_pin_remap)
|
||||
#define DT_USB_ENABLE_PIN_REMAP DT_PROP(DT_INST(0, st_stm32_usb), enable_pin_remap)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
@ -1040,11 +1042,11 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
|
|||
struct device *usb_disconnect;
|
||||
|
||||
usb_disconnect = device_get_binding(
|
||||
DT_INST_0_ST_STM32_USB_DISCONNECT_GPIOS_CONTROLLER);
|
||||
DT_GPIO_LABEL(DT_INST(0, st_stm32_usb), disconnect_gpios));
|
||||
|
||||
gpio_pin_configure(usb_disconnect,
|
||||
DT_INST_0_ST_STM32_USB_DISCONNECT_GPIOS_PIN,
|
||||
DT_INST_0_ST_STM32_USB_DISCONNECT_GPIOS_FLAGS |
|
||||
DT_GPIO_PIN(DT_INST(0, st_stm32_usb), disconnect_gpios),
|
||||
DT_GPIO_FLAGS(DT_INST(0, st_stm32_usb), disconnect_gpios) |
|
||||
(state ? GPIO_OUTPUT_ACTIVE : GPIO_OUTPUT_INACTIVE));
|
||||
}
|
||||
#endif /* USB && CONFIG_USB_DC_STM32_DISCONN_ENABLE */
|
||||
|
|
|
@ -6,6 +6,8 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT st_stm32_watchdog
|
||||
|
||||
#include <drivers/watchdog.h>
|
||||
#include <soc.h>
|
||||
#include <errno.h>
|
||||
|
@ -175,10 +177,10 @@ static int iwdg_stm32_init(struct device *dev)
|
|||
}
|
||||
|
||||
static struct iwdg_stm32_data iwdg_stm32_dev_data = {
|
||||
.Instance = (IWDG_TypeDef *)DT_INST_0_ST_STM32_WATCHDOG_BASE_ADDRESS
|
||||
.Instance = (IWDG_TypeDef *)DT_INST_REG_ADDR(0)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(iwdg_stm32, DT_INST_0_ST_STM32_WATCHDOG_LABEL,
|
||||
DEVICE_AND_API_INIT(iwdg_stm32, DT_INST_LABEL(0),
|
||||
iwdg_stm32_init, &iwdg_stm32_dev_data, NULL,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&iwdg_stm32_api);
|
||||
|
|
|
@ -4,6 +4,8 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT st_stm32_window_watchdog
|
||||
|
||||
#include <drivers/watchdog.h>
|
||||
#include <soc.h>
|
||||
#include <errno.h>
|
||||
|
@ -259,13 +261,13 @@ static struct wwdg_stm32_data wwdg_stm32_dev_data = {
|
|||
|
||||
static struct wwdg_stm32_config wwdg_stm32_dev_config = {
|
||||
.pclken = {
|
||||
.enr = DT_INST_0_ST_STM32_WINDOW_WATCHDOG_CLOCK_BITS,
|
||||
.bus = DT_INST_0_ST_STM32_WINDOW_WATCHDOG_CLOCK_BUS
|
||||
.enr = DT_INST_CLOCKS_CELL(0, bits),
|
||||
.bus = DT_INST_CLOCKS_CELL(0, bus)
|
||||
},
|
||||
.Instance = (WWDG_TypeDef *)DT_INST_0_ST_STM32_WINDOW_WATCHDOG_BASE_ADDRESS,
|
||||
.Instance = (WWDG_TypeDef *)DT_INST_REG_ADDR(0),
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(wwdg_stm32, DT_INST_0_ST_STM32_WINDOW_WATCHDOG_LABEL,
|
||||
DEVICE_AND_API_INIT(wwdg_stm32, DT_INST_LABEL(0),
|
||||
wwdg_stm32_init, &wwdg_stm32_dev_data, &wwdg_stm32_dev_config,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&wwdg_stm32_api);
|
||||
|
@ -274,9 +276,9 @@ static void wwdg_stm32_irq_config(struct device *dev)
|
|||
{
|
||||
WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
|
||||
|
||||
IRQ_CONNECT(DT_INST_0_ST_STM32_WINDOW_WATCHDOG_IRQ_0,
|
||||
DT_INST_0_ST_STM32_WINDOW_WATCHDOG_IRQ_0_PRIORITY,
|
||||
IRQ_CONNECT(DT_INST_IRQN(0),
|
||||
DT_INST_IRQ(0, priority),
|
||||
wwdg_stm32_isr, DEVICE_GET(wwdg_stm32), 0);
|
||||
irq_enable(DT_INST_0_ST_STM32_WINDOW_WATCHDOG_IRQ_0);
|
||||
irq_enable(DT_INST_IRQN(0));
|
||||
LL_WWDG_EnableIT_EWKUP(wwdg);
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue