Extend the PWM API with optional API functions for enabling DMA requests
Possible solution for #88670
Signed-off-by: Vincent Surkijn <vincent.surkijn@siemens.com>
Correct an #if which otherwise is always true, so we do not
refer to a function which does not exist otherwise.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The settings and calculations are often done in micro or nano seconds
and the result is not always shown. So, just add the period cycles as
part of the error message to get the calculated value.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
For stm32h7 the order matters to get the pwm to output the values as
expected. As reported for the the H730 doesn't produce PWM output when
the LL_TIM_OC_SetDeadTime is called after LL_TIM_EnableAllOutputs. So,
switch the order of the calls and this doesn't impact the stm32f413zh
boards.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
Clean indentation in IRQ_CONNECT_AND_ENABLE_BY_NAME(), IRQ_CONFIG_FUNC()
and IRQ_CONNECT_AND_ENABLE_DEFAULT() macros of STM32 PWM driver.
Remove a useless trailing semi column character in the interrupt function
defined with IRQ_CONFIG_FUNC() macro.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
When using an stm32 in a bridge circuit with complementary outputs,
the deadtime needs to be configurable to avoid shoot-thru current
on the circuit. So, the HAL has the configuration in the BDTR init
and use that api access to set the configuration.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
Align the definition of the complementary channels to the normal channels.
That way, it is consistent for all arrays, we use channel-1 as index, and
no other operation is necessary.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This change reduces the level of pointer indirection, which minimizes
repeated dereferencing and helps reduce the overall code size, in the same
way as commit 48e326a5520ec884f38f6a7ac4e88c59a01ceb95 for UART.
This also fixes the type complimentary -> complementary.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove the calls to LL_TIM_xx_StructInit and LL_TIM_xx_Init in the PWM
driver. This avoids calling functions from stm32xxxx_ll_tim.c.
They are replaced by a set of simpler functions from the header file.
OC Init in particular is much simpler now. The init structure needed to be
filled out with the complementary channel (if it existed), even though its
configuration didn't change.
The new init is much more direct and only touches what needs to be
modified.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function get_tim_clk.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
With the four-channel-capture-support property enabled, the STM32 PWM
driver was missing every other frames during PWM capture.
The counter values are now reset just after getting the pulse and the
period of the cycle, instead of waiting the next interrupt to do so, and
thus missing a cycle.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The clock tree of the STM32H7RS series uses the ppre1
and ppre2 naming convention instead of apb1_prescaler
and apb2_prescaler for bus prescaler.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The `LOG_ERR` will spam the log if the window is low e.g. 1 ms.
Also the PWM capture callback will be called with an error, which allows
handling and logging the error if desired.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
If the value in the period_cycles variable exceeds UINT16_MAX, a 16-bit
timer will return an error code 134. An error message was added to
indicate that the value does not fit into the 16-bit timer register.
An error message advising developers to reduce the value to 16-bit
simplifies the process, allowing them to understand immediately that
reducing the value will resolve the issue.
Signed-off-by: Marek Sroka <m.sroka14@gmail.com>
Use "const LL_TIM_IC_GetCaptureCHx" & "const LL_TIM_IsActiveFlag_CCx"
with STM32G4X series, following changes in stm32cube:stm32g4xx:drivers:
include:stm32g4xx_ll_tim.h
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Use "const LL_TIM_IC_GetCaptureCHx" & "const LL_TIM_IsActiveFlag_CCx"
with STM32F4X series, following changes in stm32cube:stm32f4xx:drivers:
include:stm32f4xx_ll_tim.h
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
When not using 4 channel capture, overflows were never reported
to the application, because the check was in the
four_channel_capture_support branch.
Signed-off-by: Fabian Pflug <fabian.pflug@grandcentrix.net>
Use "const LL_TIM_IC_GetCaptureCHx" & "const LL_TIM_IsActiveFlag_CCx"
with STM32F1X series, following changes in stm32cube:stm32f1xx:drivers:
include:stm32f1xx_ll_tim.h
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Previously the pwm capture only support capturing on channel 1
and 2, because the slave mode controller was used, which uses
the signal TIxFP which is not available for channel 3 and 4.
This commit adds optional support for four channel capturing by
changing the method of capturing PWM signals to not use the
slave mode controller to reset the counter register. Instead the
counter is reset in the ISR. This will result in a slight loss
of accuracy but is still within an acceptable range.
Co-authored-by: Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
If a timer is left running on an stm32mp1, (most likely) on the next run
the timer is stuck.
A simple timer reset before initialization fixes the issue.
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Since clocks aren't declared in the devicetree for the stm32mp1
co-processor. Read the resulting clock divider here instead.
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Some STM32 timers have more than one interrupt available.
When such timer is used it's likely that the first found interrupt
will not be the proper, 'cc' interrupt for input capture.
Existing implementation always connected the first irq, which worked
for timers with single, 'global' interrupt but broke input capture
for advanced timers with more interrupts.
Improve the IRQ connection logic by connecting the 'cc' interrupt
if it exists. Only if not found use the fallback mechanism of taking the
first index
Signed-off-by: Marek Metelski <marek@metelski.dev>
Change the name of the custom macro defined for the stm32 devices
to fit the VND_PWM_xxx model
Keeping old deprecated macro, though.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move period and pulse computation to right before
the channel enable code.
That fixes the inability to disable the channel by
providing the period of 0.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
The variable indicating the PWM channel is now names "channel" instead
of "pwm", adjust all drivers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The API call checks for this condition before calling the pin_set driver
OP call, so drivers don't have to do this check now.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
If the dts defines the PWM complementary output, then the OCN
must be init in place of the OC state and polarity.
This is an exclusive setting for this pin.
The channel in LL_TIM_OC_SetPolarity can be the complementary one.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When configuring the pwm capture, the callback function might
be reset, this i not an error. However the isr should not call it
and enabling the capture should always provide a callback function.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The PINCTRL_DT_(INST_)DEFINE macros already defined the trailing ;,
making its usage inconsistent with other macros such as
DEVICE_DT_DEFINE.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Replace usages of DT_PARENT(DT_DRV_INST(idx)) with more idiomatic
DT_INST_PARENT(idx).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use the new pinctrl API to configure pins.
Since STM32F1 series require pinctrl option and required register
address is parent timer address in place of own node register address,
use PINCTRL_DT_INST_CUSTOM_REG_DEFINE in place of usual
PINCTRL_DT_INST_DEFINE for this specific series.
Additionally, remove the automatic selection of PINMUX API.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
