0144ed6b63
Add RISCV 64bit registers and parse them in coredump script. Signed-off-by: Aleksandar Cecaric <aleksandar.cecaric@nextsilicon.com>
119 lines
2.3 KiB
C
119 lines
2.3 KiB
C
/*
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* Copyright (c) 2021 Facebook, Inc. and its affiliates
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <zephyr/debug/coredump.h>
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#ifndef CONFIG_64BIT
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#define ARCH_HDR_VER 1
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#else
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#define ARCH_HDR_VER 2
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#endif
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struct riscv_arch_block {
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#ifdef CONFIG_64BIT
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struct {
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uint64_t ra;
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uint64_t tp;
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uint64_t t0;
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uint64_t t1;
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uint64_t t2;
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uint64_t a0;
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uint64_t a1;
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uint64_t a2;
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uint64_t a3;
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uint64_t a4;
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uint64_t a5;
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uint64_t a6;
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uint64_t a7;
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uint64_t t3;
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uint64_t t4;
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uint64_t t5;
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uint64_t t6;
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uint64_t pc;
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} r;
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#else /* !CONFIG_64BIT */
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struct {
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uint32_t ra;
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uint32_t tp;
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uint32_t t0;
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uint32_t t1;
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uint32_t t2;
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uint32_t a0;
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uint32_t a1;
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uint32_t a2;
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uint32_t a3;
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uint32_t a4;
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uint32_t a5;
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#if !defined(CONFIG_RISCV_ISA_RV32E)
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uint32_t a6;
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uint32_t a7;
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uint32_t t3;
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uint32_t t4;
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uint32_t t5;
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uint32_t t6;
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#endif /* !CONFIG_RISCV_ISA_RV32E */
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uint32_t pc;
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} r;
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#endif /* CONFIG_64BIT */
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} __packed;
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/*
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* This might be too large for stack space if defined
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* inside function. So do it here.
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*/
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static struct riscv_arch_block arch_blk;
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void arch_coredump_info_dump(const z_arch_esf_t *esf)
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{
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struct coredump_arch_hdr_t hdr = {
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.id = COREDUMP_ARCH_HDR_ID,
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.hdr_version = ARCH_HDR_VER,
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.num_bytes = sizeof(arch_blk),
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};
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/* Nothing to process */
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if (esf == NULL) {
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return;
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}
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(void)memset(&arch_blk, 0, sizeof(arch_blk));
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/*
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* 33 registers expected by GDB. Not all are in ESF but the GDB stub will need
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* to send all 33 as one packet. The stub will need to send undefined for
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* registers not presented in coredump.
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*/
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arch_blk.r.ra = esf->ra;
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arch_blk.r.t0 = esf->t0;
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arch_blk.r.t1 = esf->t1;
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arch_blk.r.t2 = esf->t2;
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arch_blk.r.a0 = esf->a0;
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arch_blk.r.a1 = esf->a1;
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arch_blk.r.a2 = esf->a2;
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arch_blk.r.a3 = esf->a3;
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arch_blk.r.a4 = esf->a4;
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arch_blk.r.a5 = esf->a5;
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#if !defined(CONFIG_RISCV_ISA_RV32E)
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arch_blk.r.t3 = esf->t3;
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arch_blk.r.t4 = esf->t4;
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arch_blk.r.t5 = esf->t5;
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arch_blk.r.t6 = esf->t6;
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arch_blk.r.a6 = esf->a6;
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arch_blk.r.a7 = esf->a7;
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#endif /* !CONFIG_RISCV_ISA_RV32E */
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arch_blk.r.pc = esf->mepc;
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/* Send for output */
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coredump_buffer_output((uint8_t *)&hdr, sizeof(hdr));
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coredump_buffer_output((uint8_t *)&arch_blk, sizeof(arch_blk));
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}
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uint16_t arch_coredump_tgt_code_get(void)
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{
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return COREDUMP_TGT_RISC_V;
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}
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