Commit graph

5 commits

Author SHA1 Message Date
Aleksandar Cecaric 0144ed6b63 arch: riscv: update coredump for 64BIT RISCV
Add RISCV 64bit registers and parse them in coredump script.

Signed-off-by: Aleksandar Cecaric <aleksandar.cecaric@nextsilicon.com>
2024-04-13 07:03:23 -04:00
Carlo Caione 673f41e708 riscv: Introduce support for RV32E
Introduce support for RV32E.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-08 18:50:22 +09:00
Gerard Marull-Paretas 16811660ee arch: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all arch code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:22 +02:00
Nicolas Pitre 247d2c8e3b riscv: move the tp register from caller-saved to callee-saved
This is a per-thread register that gets updated only when context
switching. No need to load and save it on every exception entry.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-03-21 07:28:05 -04:00
Mark Holden 1a697ccf59 coredump: add support for RISC-V
This adds the necessary bits in arch code, and Python scripts
to enable coredump support for RISC-V

Signed-off-by: Mark Holden <mholden@fb.com>
2021-12-08 08:54:32 -05:00