zephyr/arch/riscv/core
Yong Cong Sin a82a54cd38 arch: riscv: remove unnecessary cast
Remove unnecessary cast of `fp` into `uintptr_t`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-16 09:20:19 +02:00
..
offsets arch: riscv: print callee-saved-registers in fatal error 2024-04-24 15:57:40 -04:00
asm_macros.inc riscv: abstract RV32E register access 2022-06-23 13:12:05 -04:00
CMakeLists.txt riscv: integrate the new FPU context switching support 2023-01-24 15:26:18 +01:00
coredump.c arch: riscv: update coredump for 64BIT RISCV 2024-04-13 07:03:23 -04:00
cpu_idle.c arch: riscv: disable interrupts before wfi 2024-03-21 14:30:15 +01:00
fatal.c arch: riscv: remove unnecessary cast 2024-05-16 09:20:19 +02:00
fpu.c arch: smp: make flush_fpu_ipi a common, optional interfaces 2024-01-09 10:00:17 +01:00
fpu.S riscv: smarter FPU context switching support 2023-01-24 15:26:18 +01:00
irq_manage.c arch: riscv: irq_manage: support ISR_OFFSET in dynamic IRQs 2024-04-25 15:03:23 +02:00
irq_offload.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
isr.S arch: riscv: apply CONFIG_RISCV_MCAUSE_EXCEPTION_MASK to FPU code 2024-05-14 09:32:39 +02:00
pmp.c coding guidelines: comply with MISRA Rule 11.8 2024-05-09 10:28:44 +02:00
pmp.S include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
prep_c.c arch: riscv: define local soc_interrupt_init prototypes 2024-01-15 09:58:03 +01:00
reboot.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reset.S arch: introduce arch_secondary_cpu_init 2024-01-09 10:00:17 +01:00
semihost.c arch: riscv: Align semihost_exec function at 16-byte boundary 2022-08-08 10:52:34 +02:00
smp.c kernel: rename Z_KERNEL_STACK_BUFFER to K_KERNEL_STACK_BUFFER 2024-03-27 19:27:10 -04:00
switch.S riscv: integrate the new FPU context switching support 2023-01-24 15:26:18 +01:00
thread.c kernel: rename Z_THREAD_STACK_BUFFER to K_THREAD_STACK_BUFFER 2024-03-27 19:27:10 -04:00
tls.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
userspace.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
vector_table.ld arch: riscv: core: Place vectors section through zephyr_linker_sources() 2022-09-08 10:39:31 +02:00