arch: riscv: apply CONFIG_RISCV_MCAUSE_EXCEPTION_MASK to FPU code
Some implementations use bits outside of the mcause mask for other purpose. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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@ -203,6 +203,8 @@ SECTION_FUNC(exception.entry, _isr_wrapper)
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bnez t1, no_fp
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/* determine if this is an Illegal Instruction exception */
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csrr t2, mcause
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li t1, CONFIG_RISCV_MCAUSE_EXCEPTION_MASK
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and t2, t2, t1
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li t1, 2 /* 2 = illegal instruction */
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bne t1, t2, no_fp
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/* determine if we trapped on an FP instruction. */
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