189cd1f4a2
The cache operations must be quick, optimized and possibly inlined. The current API is clunky, functions are not inlined and passing parameters around that are basically always known at compile time. In this patch we rework the cache functions to allow us to get rid of useless parameters and make inlining easier. In particular this changeset is doing three things: 1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and `CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE` 2. The cache API has been reworked. 3. Comments are added. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
942 lines
29 KiB
Plaintext
942 lines
29 KiB
Plaintext
# General architecture configuration options
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# Copyright (c) 2015 Intel Corporation
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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# Include these first so that any properties (e.g. defaults) below can be
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# overridden (by defining symbols in multiple locations)
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# Note: $ARCH might be a glob pattern
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source "$(ARCH_DIR)/$(ARCH)/Kconfig"
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# Architecture symbols
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#
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# Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
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# by SOC_*.
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config ARC
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bool
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select ARCH_IS_SET
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select HAS_DTS
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imply XIP
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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help
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ARC architecture
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config ARM
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bool
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select ARCH_IS_SET
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select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M
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select HAS_DTS
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# FIXME: current state of the code for all ARM requires this, but
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# is really only necessary for Cortex-M with ARM MPU!
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select GEN_PRIV_STACKS
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select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M || CPU_AARCH32_CORTEX_A
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help
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ARM architecture
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config ARM64
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bool
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select ARCH_IS_SET
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select 64BIT
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select HAS_DTS
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select HAS_ARM_SMCCC
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
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help
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ARM64 (AArch64) architecture
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config MIPS
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bool
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select ARCH_IS_SET
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select ATOMIC_OPERATIONS_C
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select HAS_DTS
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help
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MIPS architecture
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config SPARC
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bool
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select ARCH_IS_SET
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select HAS_DTS
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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select BIG_ENDIAN
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select ATOMIC_OPERATIONS_BUILTIN if SPARC_CASA
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select ATOMIC_OPERATIONS_C if !SPARC_CASA
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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select ARCH_HAS_EXTRA_EXCEPTION_INFO
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help
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SPARC architecture
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config X86
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bool
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select ARCH_IS_SET
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select ATOMIC_OPERATIONS_BUILTIN
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select HAS_DTS
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select ARCH_SUPPORTS_COREDUMP
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select CPU_HAS_MMU
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select ARCH_MEM_DOMAIN_DATA if USERSPACE && !X86_COMMON_PAGE_TABLE
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select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
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select ARCH_HAS_GDBSTUB if !X86_64
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select ARCH_HAS_TIMING_FUNCTIONS
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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select ARCH_HAS_DEMAND_PAGING
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select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
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select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \
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&& !BOARD_HAS_TIMING_FUNCTIONS \
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&& !SOC_HAS_TIMING_FUNCTIONS
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help
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x86 architecture
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config NIOS2
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bool
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select ARCH_IS_SET
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select ATOMIC_OPERATIONS_C
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select HAS_DTS
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imply XIP
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select ARCH_HAS_TIMING_FUNCTIONS
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help
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Nios II Gen 2 architecture
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config RISCV
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bool
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select ARCH_IS_SET
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select HAS_DTS
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select ARCH_SUPPORTS_COREDUMP
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select ARCH_HAS_CODE_DATA_RELOCATION
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
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select USE_SWITCH_SUPPORTED
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select USE_SWITCH
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select SCHED_IPI_SUPPORTED if SMP
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imply XIP
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help
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RISCV architecture
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config XTENSA
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bool
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select ARCH_IS_SET
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select HAS_DTS
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
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select ARCH_HAS_CODE_DATA_RELOCATION
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select ARCH_HAS_TIMING_FUNCTIONS
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imply ATOMIC_OPERATIONS_ARCH
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help
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Xtensa architecture
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config ARCH_POSIX
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bool
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select ARCH_IS_SET
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select HAS_DTS
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select ATOMIC_OPERATIONS_BUILTIN
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select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
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select ARCH_HAS_CUSTOM_BUSY_WAIT
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select ARCH_HAS_THREAD_ABORT
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select NATIVE_APPLICATION
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select HAS_COVERAGE_SUPPORT
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help
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POSIX (native) architecture
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config ARCH_IS_SET
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bool
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help
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Helper symbol to detect SoCs forgetting to select one of the arch
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symbols above. See the top-level CMakeLists.txt.
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menu "General Architecture Options"
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source "arch/common/Kconfig"
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module = ARCH
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module-str = arch
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source "subsys/logging/Kconfig.template.log_config"
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config BIG_ENDIAN
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bool
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help
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This option tells the build system that the target system is big-endian.
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Little-endian architecture is the default and should leave this option
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unselected. This option is selected by arch/$ARCH/Kconfig,
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soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid
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modifying it. The option is used to select linker script OUTPUT_FORMAT
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and command line option for gen_isr_tables.py.
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config LITTLE_ENDIAN
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# Hidden Kconfig option representing the default little-endian architecture
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# This is just the opposite of BIG_ENDIAN and is used for non-negative
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# conditional compilation
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bool
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depends on !BIG_ENDIAN
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default y
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config 64BIT
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bool
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help
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This option tells the build system that the target system is
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using a 64-bit address space, meaning that pointer and long types
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are 64 bits wide. This option is selected by arch/$ARCH/Kconfig,
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soc/**/Kconfig, or boards/**/Kconfig and the user should generally
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avoid modifying it.
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_SRAM := zephyr,sram
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config SRAM_SIZE
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int "SRAM Size in kB"
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K)
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help
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The SRAM size in kB. The default value comes from /chosen/zephyr,sram in
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devicetree. The user should generally avoid changing it via menuconfig or
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in configuration files.
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config SRAM_BASE_ADDRESS
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hex "SRAM Base Address"
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))
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help
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The SRAM base address. The default value comes from from
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/chosen/zephyr,sram in devicetree. The user should generally avoid
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changing it via menuconfig or in configuration files.
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if ARC || ARM || ARM64 || NIOS2 || X86
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_FLASH := zephyr,flash
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config FLASH_SIZE
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int "Flash Size in kB"
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && (ARM ||ARM64)) || !ARM
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help
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This option specifies the size of the flash in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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it via the menu configuration.
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config FLASH_BASE_ADDRESS
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hex "Flash Base Address"
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && (ARM || ARM64)) || !ARM
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help
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This option specifies the base address of the flash on the board. It is
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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endif # ARM || ARM64 || ARC || NIOS2 || X86
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if ARCH_HAS_TRUSTED_EXECUTION
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config TRUSTED_EXECUTION_SECURE
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bool "Trusted Execution: Secure firmware image"
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help
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Select this option to enable building a Secure firmware
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image for a platform that supports Trusted Execution. A
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Secure firmware image will execute in Secure state. It may
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allow the CPU to execute in Non-Secure (Normal) state.
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Therefore, a Secure firmware image shall be able to
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configure security attributions of CPU resources (memory
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areas, peripherals, interrupts, etc.) as well as to handle
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faults, related to security violations. It may optionally
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allow certain functions to be called from the Non-Secure
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(Normal) domain.
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config TRUSTED_EXECUTION_NONSECURE
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depends on !TRUSTED_EXECUTION_SECURE
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bool "Trusted Execution: Non-Secure firmware image"
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help
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Select this option to enable building a Non-Secure
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firmware image for a platform that supports Trusted
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Execution. A Non-Secure firmware image will execute
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in Non-Secure (Normal) state. Therefore, it shall not
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access CPU resources (memory areas, peripherals,
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interrupts etc.) belonging to the Secure domain.
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endif # ARCH_HAS_TRUSTED_EXECUTION
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config HW_STACK_PROTECTION
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bool "Hardware Stack Protection"
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depends on ARCH_HAS_STACK_PROTECTION
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help
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Select this option to enable hardware-based platform features to
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catch stack overflows when the system is running in privileged
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mode. If CONFIG_USERSPACE is not enabled, the system is always
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running in privileged mode.
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Note that this does not necessarily prevent corruption and assertions
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about the overall system state when a fault is triggered cannot be
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made.
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config USERSPACE
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bool "User mode threads"
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depends on ARCH_HAS_USERSPACE
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depends on RUNTIME_ERROR_CHECKS
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depends on SRAM_REGION_PERMISSIONS
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select THREAD_STACK_INFO
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help
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When enabled, threads may be created or dropped down to user mode,
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which has significantly restricted permissions and must interact
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with the kernel via system calls. See Zephyr documentation for more
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details about this feature.
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If a user thread overflows its stack, this will be caught and the
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kernel itself will be shielded from harm. Enabling this option
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may or may not catch stack overflows when the system is in
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privileged mode or handling a system call; to ensure these are always
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caught, enable CONFIG_HW_STACK_PROTECTION.
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config PRIVILEGED_STACK_SIZE
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int "Size of privileged stack"
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default 1024
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depends on ARCH_HAS_USERSPACE
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help
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This option sets the privileged stack region size that will be used
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in addition to the user mode thread stack. During normal execution,
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this region will be inaccessible from user mode. During system calls,
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this region will be utilized by the system call. This value must be
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a multiple of the minimum stack alignment.
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config KOBJECT_TEXT_AREA
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int "Size of kobject text area"
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default 512 if COVERAGE_GCOV
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default 512 if NO_OPTIMIZATIONS
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default 512 if STACK_CANARIES && RISCV
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default 256
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depends on ARCH_HAS_USERSPACE
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help
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Size of kernel object text area. Used in linker script.
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config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT
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int "Reserve extra kobject data area (in percentage)"
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default 100
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depends on ARCH_HAS_USERSPACE
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help
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Multiplication factor used to calculate the size of placeholder to
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reserve space for kobject metadata hash table. The hash table is
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generated via gperf is highly dependent on the absolute addresses of
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kobjects which might change between prebuilts. To reserve enough
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space for the hash table during final linking passes to keep
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kobjects in same place, the size of reserved space is calculated
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from the first prebuilt plus additional space calculated with
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this percentage (of the kobject data area in first prebuilt).
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config KOBJECT_RODATA_AREA_EXTRA_BYTES
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int "Reserve extra bytes for kobject rodata area"
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default 16
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depends on ARCH_HAS_USERSPACE
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help
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Reserve a few more bytes for the RODATA region for kobject metadata.
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This is to account for the uncertainty of tables generated by gperf.
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config GEN_PRIV_STACKS
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bool
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help
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Selected if the architecture requires that privilege elevation stacks
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be allocated in a separate memory area. This is typical of arches
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whose MPUs require regions to be power-of-two aligned/sized.
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FIXME: This should be removed and replaced with checks against
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CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT, but both ARM and ARC
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changes will be necessary for this.
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config STACK_GROWS_UP
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bool "Stack grows towards higher memory addresses"
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help
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Select this option if the architecture has upward growing thread
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stacks. This is not common.
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config NO_UNUSED_STACK_INSPECTION
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bool
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help
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Selected if the architecture will generate a fault if unused stack
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memory is examined, which is the region between the current stack
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pointer and the deepest available address in the current stack
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region.
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config MAX_THREAD_BYTES
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int "Bytes to use when tracking object thread permissions"
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default 2
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depends on USERSPACE
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help
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Every kernel object will have an associated bitfield to store
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thread permissions for that object. This controls the size of the
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bitfield (in bytes) and imposes a limit on how many threads can
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be created in the system.
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config DYNAMIC_OBJECTS
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bool "Allow kernel objects to be allocated at runtime"
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depends on USERSPACE
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help
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Enabling this option allows for kernel objects to be requested from
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the calling thread's resource pool, at a slight cost in performance
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due to the supplemental run-time tables required to validate such
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objects.
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Objects allocated in this way can be freed with a supervisor-only
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API call, or when the number of references to that object drops to
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zero.
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config NOCACHE_MEMORY
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bool "Support for uncached memory"
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depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT
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help
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Add a "nocache" read-write memory section that is configured to
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not be cached. This memory section can be used to perform DMA
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transfers when cache coherence issues are not optimal or can not
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be solved using cache maintenance operations.
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menu "Interrupt Configuration"
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config DYNAMIC_INTERRUPTS
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bool "Installation of IRQs at runtime"
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help
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Enable installation of interrupts at runtime, which will move some
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interrupt-related data structures to RAM instead of ROM, and
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on some architectures increase code size.
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config GEN_ISR_TABLES
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bool "Use generated IRQ tables"
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help
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This option controls whether a platform uses the gen_isr_tables
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script to generate its interrupt tables. This mechanism will create
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an appropriate hardware vector table and/or software IRQ table.
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config GEN_IRQ_VECTOR_TABLE
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bool "Generate an interrupt vector table"
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default y
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depends on GEN_ISR_TABLES
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help
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This option controls whether a platform using gen_isr_tables
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needs an interrupt vector table created. Only disable this if the
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platform does not use a vector table at all, or requires the vector
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table to be in a format that is not an array of function pointers
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indexed by IRQ line. In the latter case, the vector table must be
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supplied by the application or architecture code.
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config ARCH_IRQ_VECTOR_TABLE_ALIGN
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int "Alignment size of the interrupt vector table"
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default 4
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depends on GEN_IRQ_VECTOR_TABLE
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help
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This option controls alignment size of generated
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_irq_vector_table. Some architecture needs an IRQ vector table
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to be aligned to architecture specific size. The default
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size is 0 for no alignment.
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choice IRQ_VECTOR_TABLE_TYPE
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prompt "IRQ vector table type"
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depends on GEN_IRQ_VECTOR_TABLE
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default IRQ_VECTOR_TABLE_JUMP_BY_CODE if (RISCV && !RISCV_HAS_CLIC)
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default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS
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config IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS
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bool "Jump by address"
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help
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The IRQ vector table contains the address of the interrupt handler.
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config IRQ_VECTOR_TABLE_JUMP_BY_CODE
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bool "Jump by code"
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help
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The IRQ vector table contains the opcode of a jump instruction to the
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interrupt handler address.
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endchoice
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config GEN_SW_ISR_TABLE
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bool "Generate a software ISR table"
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default y
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depends on GEN_ISR_TABLES
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help
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This option controls whether a platform using gen_isr_tables
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needs a software ISR table table created. This is an array of struct
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_isr_table_entry containing the interrupt service routine and supplied
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parameter.
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config ARCH_SW_ISR_TABLE_ALIGN
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int "Alignment size of a software ISR table"
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default 4
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depends on GEN_SW_ISR_TABLE
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help
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This option controls alignment size of generated
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_sw_isr_table. Some architecture needs a software ISR table
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to be aligned to architecture specific size. The default
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size is 0 for no alignment.
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config GEN_IRQ_START_VECTOR
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int
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default 0
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depends on GEN_ISR_TABLES
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help
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On some architectures, part of the vector table may be reserved for
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system exceptions and is declared separately from the tables
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created by gen_isr_tables.py. When creating these tables, this value
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will be subtracted from CONFIG_NUM_IRQS to properly size them.
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This is a hidden option which needs to be set per architecture and
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left alone.
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config IRQ_OFFLOAD
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bool "IRQ offload"
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depends on TEST
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help
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Enable irq_offload() API which allows functions to be synchronously
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run in interrupt context. Only useful for test cases that need
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to validate the correctness of kernel objects in IRQ context.
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config IRQ_OFFLOAD_NESTED
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bool "irq_offload() supports nested IRQs"
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depends on IRQ_OFFLOAD
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help
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When set by the arch layer, indicates that irq_offload() may
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legally be called in interrupt context to cause a
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synchronous nested interrupt on the current CPU. Not all
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hardware is capable.
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config EXTRA_EXCEPTION_INFO
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bool "Collect extra exception info"
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depends on ARCH_HAS_EXTRA_EXCEPTION_INFO
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help
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This option enables the collection of extra information, such as
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register state, when a fault occurs. This information can be useful
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to collect for post-mortem analysis and debug of issues.
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endmenu # Interrupt configuration
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config INIT_ARCH_HW_AT_BOOT
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bool "Initialize internal architecture state at boot"
|
|
depends on ARCH_SUPPORTS_ARCH_HW_INIT
|
|
help
|
|
This option instructs Zephyr to force the initialization
|
|
of the internal architectural state (for example ARCH-level
|
|
HW registers and system control blocks) during boot to
|
|
the reset values as specified by the corresponding
|
|
architecture manual. The option is useful when the Zephyr
|
|
firmware image is chain-loaded, for example, by a debugger
|
|
or a bootloader, and we need to guarantee that the internal
|
|
states of the architecture core blocks are restored to the
|
|
reset values (as specified by the architecture).
|
|
|
|
Note: the functionality is architecture-specific. For the
|
|
implementation details refer to each architecture where
|
|
this feature is supported.
|
|
|
|
endmenu
|
|
|
|
#
|
|
# Architecture Capabilities
|
|
#
|
|
|
|
config ARCH_HAS_SINGLE_THREAD_SUPPORT
|
|
bool
|
|
|
|
config ARCH_HAS_TIMING_FUNCTIONS
|
|
bool
|
|
|
|
config ARCH_HAS_TRUSTED_EXECUTION
|
|
bool
|
|
|
|
config ARCH_HAS_STACK_PROTECTION
|
|
bool
|
|
|
|
config ARCH_HAS_USERSPACE
|
|
bool
|
|
|
|
config ARCH_HAS_EXECUTABLE_PAGE_BIT
|
|
bool
|
|
|
|
config ARCH_HAS_NOCACHE_MEMORY_SUPPORT
|
|
bool
|
|
|
|
config ARCH_HAS_RAMFUNC_SUPPORT
|
|
bool
|
|
|
|
config ARCH_HAS_NESTED_EXCEPTION_DETECTION
|
|
bool
|
|
|
|
config ARCH_SUPPORTS_COREDUMP
|
|
bool
|
|
|
|
config ARCH_SUPPORTS_ARCH_HW_INIT
|
|
bool
|
|
|
|
config ARCH_HAS_EXTRA_EXCEPTION_INFO
|
|
bool
|
|
|
|
config ARCH_HAS_GDBSTUB
|
|
bool
|
|
|
|
config ARCH_HAS_COHERENCE
|
|
bool
|
|
help
|
|
When selected, the architecture supports the
|
|
arch_mem_coherent() API and can link into incoherent/cached
|
|
memory using the ".cached" linker section.
|
|
|
|
config ARCH_HAS_THREAD_LOCAL_STORAGE
|
|
bool
|
|
|
|
config ARCH_HAS_SUSPEND_TO_RAM
|
|
bool
|
|
help
|
|
When selected, the architecture supports suspend-to-RAM (S2RAM).
|
|
|
|
#
|
|
# Other architecture related options
|
|
#
|
|
|
|
config ARCH_HAS_THREAD_ABORT
|
|
bool
|
|
|
|
config ARCH_HAS_CODE_DATA_RELOCATION
|
|
bool
|
|
help
|
|
When selected, the architecture/SoC implements support for
|
|
CODE_DATA_RELOCATION in its linker scripts.
|
|
|
|
#
|
|
# Hidden CPU family configs
|
|
#
|
|
|
|
config CPU_HAS_TEE
|
|
bool
|
|
help
|
|
This option is enabled when the CPU has support for Trusted
|
|
Execution Environment (e.g. when it has a security attribution
|
|
unit).
|
|
|
|
config CPU_HAS_DCLS
|
|
bool
|
|
help
|
|
This option is enabled when the processor hardware has support for
|
|
Dual-redundant Core Lock-step (DCLS) topology.
|
|
|
|
config CPU_HAS_FPU
|
|
bool
|
|
help
|
|
This option is enabled when the CPU has hardware floating point
|
|
unit.
|
|
|
|
config CPU_HAS_FPU_DOUBLE_PRECISION
|
|
bool
|
|
select CPU_HAS_FPU
|
|
help
|
|
When enabled, this indicates that the CPU has a double floating point
|
|
precision unit.
|
|
|
|
config CPU_HAS_MPU
|
|
bool
|
|
help
|
|
This option is enabled when the CPU has a Memory Protection Unit (MPU).
|
|
|
|
config CPU_HAS_MMU
|
|
bool
|
|
help
|
|
This hidden option is selected when the CPU has a Memory Management Unit
|
|
(MMU).
|
|
|
|
config ARCH_HAS_DEMAND_PAGING
|
|
bool
|
|
help
|
|
This hidden configuration should be selected by the architecture if
|
|
demand paging is supported.
|
|
|
|
config ARCH_HAS_RESERVED_PAGE_FRAMES
|
|
bool
|
|
help
|
|
This hidden configuration should be selected by the architecture if
|
|
certain RAM page frames need to be marked as reserved and never used for
|
|
memory mappings. The architecture will need to implement
|
|
arch_reserved_pages_update().
|
|
|
|
config CPU_HAS_DCACHE
|
|
bool
|
|
help
|
|
This hidden configuration should be selected when the CPU has a d-cache.
|
|
|
|
config CPU_HAS_ICACHE
|
|
bool
|
|
help
|
|
This hidden configuration should be selected when the CPU has an i-cache.
|
|
|
|
config ARCH_MAPS_ALL_RAM
|
|
bool
|
|
help
|
|
This hidden option is selected by the architecture to inform the kernel
|
|
that all RAM is mapped at boot, and not just the bounds of the Zephyr image.
|
|
If RAM starts at 0x0, the first page must remain un-mapped to catch NULL
|
|
pointer dereferences. With this enabled, the kernel will not assume that
|
|
virtual memory addresses past the kernel image are available for mappings,
|
|
but instead takes into account an entire RAM mapping instead.
|
|
|
|
This is typically set by architectures which need direct access to all memory.
|
|
It is the architecture's responsibility to mark reserved memory regions
|
|
as such in arch_reserved_pages_update().
|
|
|
|
Although the kernel will not disturb this RAM mapping by re-mapping the associated
|
|
virtual addresses elsewhere, this is limited to only management of the
|
|
virtual address space. The kernel's page frame ontology will not consider
|
|
this mapping at all; non-kernel pages will be considered free (unless marked
|
|
as reserved) and Z_PAGE_FRAME_MAPPED will not be set.
|
|
|
|
config DCLS
|
|
bool "Processor is configured in DCLS mode"
|
|
depends on CPU_HAS_DCLS
|
|
default y
|
|
help
|
|
This option is enabled when the processor hardware is configured in
|
|
Dual-redundant Core Lock-step (DCLS) topology. For the processor that
|
|
supports DCLS, but is configured in split-lock mode (by default or
|
|
changed at flash time), this option should be disabled.
|
|
|
|
menuconfig MPU
|
|
bool "MPU features"
|
|
depends on CPU_HAS_MPU
|
|
help
|
|
This option, when enabled, indicates to the core kernel that an MPU
|
|
is enabled.
|
|
|
|
if MPU
|
|
module = MPU
|
|
module-str = mpu
|
|
source "subsys/logging/Kconfig.template.log_config"
|
|
|
|
config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
|
|
bool
|
|
help
|
|
This option is enabled when the MPU requires a power of two alignment
|
|
and size for MPU regions.
|
|
|
|
config MPU_REQUIRES_NON_OVERLAPPING_REGIONS
|
|
bool
|
|
help
|
|
This option is enabled when the MPU requires the active (i.e. enabled)
|
|
MPU regions to be non-overlapping with each other.
|
|
|
|
config MPU_GAP_FILLING
|
|
bool "Force MPU to be filling in background memory regions"
|
|
depends on MPU_REQUIRES_NON_OVERLAPPING_REGIONS
|
|
default y if !USERSPACE
|
|
help
|
|
This Kconfig option instructs the MPU driver to enforce
|
|
a full kernel SRAM partitioning, when it programs the
|
|
dynamic MPU regions (user thread stack, PRIV stack guard
|
|
and application memory domains) during context-switch. We
|
|
allow this to be a configurable option, in order to be able
|
|
to switch the option off and have an increased number of MPU
|
|
regions available for application memory domain programming.
|
|
|
|
Notes:
|
|
An increased number of MPU regions should only be required,
|
|
when building with USERSPACE support. As a result, when we
|
|
build without USERSPACE support, gap filling should always
|
|
be required.
|
|
|
|
When the option is switched off, access to memory areas not
|
|
covered by explicit MPU regions is restricted to privileged
|
|
code on an ARCH-specific basis. Refer to ARCH-specific
|
|
documentation for more information on how this option is
|
|
used.
|
|
|
|
endif # MPU
|
|
|
|
config SRAM_REGION_PERMISSIONS
|
|
bool "Assign appropriate permissions to kernel areas in SRAM"
|
|
depends on MMU || MPU
|
|
default y
|
|
help
|
|
This option indicates that memory protection hardware
|
|
is present, enabled, and regions have been configured at boot for memory
|
|
ranges within the kernel image.
|
|
|
|
If this option is turned on, certain areas of the kernel image will
|
|
have the following access policies applied for all threads, including
|
|
supervisor threads:
|
|
|
|
1) All program text will be have read-only, execute memory permission
|
|
2) All read-only data will have read-only permission, and execution
|
|
disabled if the hardware supports it.
|
|
3) All other RAM addresses will have read-write permission, and
|
|
execution disabled if the hardware supports it.
|
|
|
|
Options such as USERSPACE or HW_STACK_PROTECTION may additionally
|
|
impose additional policies on the memory map, which may be global
|
|
or local to the current running thread.
|
|
|
|
This option may consume additional memory to satisfy memory protection
|
|
hardware alignment constraints.
|
|
|
|
If this option is disabled, the entire kernel will have default memory
|
|
access permissions set, typically read/write/execute. It may be desirable
|
|
to turn this off on MMU systems which are using the MMU for demand
|
|
paging, do not need memory protection, and would rather not use up
|
|
RAM for the alignment between regions.
|
|
|
|
config CODE_DATA_RELOCATION
|
|
bool "Support code/data section relocation"
|
|
depends on ARCH_HAS_CODE_DATA_RELOCATION
|
|
help
|
|
Enable support for relocating .text, data and .bss sections from specified
|
|
files and placing them in a chosen memory region. Files to relocate and
|
|
the target regions should be specified in CMakeLists.txt using
|
|
zephyr_code_relocate().
|
|
|
|
menu "Floating Point Options"
|
|
|
|
config FPU
|
|
bool "Floating point unit (FPU)"
|
|
depends on CPU_HAS_FPU
|
|
help
|
|
This option enables the hardware Floating Point Unit (FPU), in order to
|
|
support using the floating point registers and instructions.
|
|
|
|
When this option is enabled, by default, threads may use the floating
|
|
point registers only in an exclusive manner, and this usually means that
|
|
only one thread may perform floating point operations.
|
|
|
|
If it is necessary for multiple threads to perform concurrent floating
|
|
point operations, the "FPU register sharing" option must be enabled to
|
|
preserve the floating point registers across context switches.
|
|
|
|
Note that this option cannot be selected for the platforms that do not
|
|
include a hardware floating point unit; the floating point support for
|
|
those platforms is dependent on the availability of the toolchain-
|
|
provided software floating point library.
|
|
|
|
config FPU_SHARING
|
|
bool "FPU register sharing"
|
|
depends on FPU && MULTITHREADING
|
|
help
|
|
This option enables preservation of the hardware floating point registers
|
|
across context switches to allow multiple threads to perform concurrent
|
|
floating point operations.
|
|
|
|
Note that some compiler configurations may activate a floating point
|
|
context by generating FP instructions for any thread, and that
|
|
context must be preserved when switching such threads in and out.
|
|
The developers can still disable the FP sharing mode in their
|
|
application projects, and switch to Unshared FP registers mode,
|
|
if it is guaranteed that the image code does not generate FP
|
|
instructions outside the single thread context that is allowed
|
|
to do so.
|
|
|
|
endmenu
|
|
|
|
menu "Cache Options"
|
|
|
|
config DCACHE
|
|
bool "Data cache (d-cache) support"
|
|
depends on CPU_HAS_DCACHE
|
|
default y
|
|
help
|
|
This option enables the support for the data cache (d-cache).
|
|
|
|
config ICACHE
|
|
bool "Instruction cache (i-cache) support"
|
|
depends on CPU_HAS_ICACHE
|
|
default y
|
|
help
|
|
This option enables the support for the instruction cache (i-cache).
|
|
|
|
config CACHE_MANAGEMENT
|
|
bool "Cache management features"
|
|
depends on DCACHE || ICACHE
|
|
help
|
|
This option enables the cache management functions backed by arch or
|
|
driver code.
|
|
|
|
config DCACHE_LINE_SIZE_DETECT
|
|
bool "Detect d-cache line size at runtime"
|
|
depends on CACHE_MANAGEMENT && DCACHE
|
|
help
|
|
This option enables querying some architecture-specific hardware for
|
|
finding the d-cache line size at the expense of taking more memory and
|
|
code and a slightly increased boot time.
|
|
|
|
If the CPU's d-cache line size is known in advance, disable this option and
|
|
manually enter the value for DCACHE_LINE_SIZE or set it in the DT
|
|
using the 'd-cache-line-size' property.
|
|
|
|
config DCACHE_LINE_SIZE
|
|
int "d-cache line size"
|
|
depends on CACHE_MANAGEMENT && DCACHE && !DCACHE_LINE_SIZE_DETECT
|
|
default 0
|
|
help
|
|
Size in bytes of a CPU d-cache line. If this is set to 0 the value is
|
|
obtained from the 'd-cache-line-size' DT property instead if present.
|
|
|
|
|
|
Detect automatically at runtime by selecting DCACHE_LINE_SIZE_DETECT.
|
|
|
|
config ICACHE_LINE_SIZE_DETECT
|
|
bool "Detect i-cache line size at runtime"
|
|
depends on CACHE_MANAGEMENT && ICACHE
|
|
help
|
|
This option enables querying some architecture-specific hardware for
|
|
finding the i-cache line size at the expense of taking more memory and
|
|
code and a slightly increased boot time.
|
|
|
|
If the CPU's i-cache line size is known in advance, disable this option and
|
|
manually enter the value for ICACHE_LINE_SIZE or set it in the DT
|
|
using the 'i-cache-line-size' property.
|
|
|
|
config ICACHE_LINE_SIZE
|
|
int "i-cache line size"
|
|
depends on CACHE_MANAGEMENT && ICACHE && !ICACHE_LINE_SIZE_DETECT
|
|
default 0
|
|
help
|
|
Size in bytes of a CPU i-cache line. If this is set to 0 the value is
|
|
obtained from the 'i-cache-line-size' DT property instead if present.
|
|
|
|
Detect automatically at runtime by selecting ICACHE_LINE_SIZE_DETECT.
|
|
|
|
choice CACHE_TYPE
|
|
prompt "Cache type"
|
|
depends on CACHE_MANAGEMENT
|
|
default ARCH_CACHE
|
|
|
|
config ARCH_CACHE
|
|
bool "Integrated cache controller"
|
|
help
|
|
Integrated on-core cache controller
|
|
|
|
config EXTERNAL_CACHE
|
|
bool "External cache controller"
|
|
help
|
|
External cache controller
|
|
|
|
endchoice
|
|
|
|
endmenu
|
|
|
|
config ARCH
|
|
string
|
|
help
|
|
System architecture string.
|
|
|
|
config SOC
|
|
string
|
|
help
|
|
SoC name which can be found under soc/<arch>/<soc name>.
|
|
This option holds the directory name used by the build system to locate
|
|
the correct linker and header files for the SoC.
|
|
|
|
config SOC_SERIES
|
|
string
|
|
help
|
|
SoC series name which can be found under soc/<arch>/<family>/<series>.
|
|
This option holds the directory name used by the build system to locate
|
|
the correct linker and header files.
|
|
|
|
config SOC_FAMILY
|
|
string
|
|
help
|
|
SoC family name which can be found under soc/<arch>/<family>.
|
|
This option holds the directory name used by the build system to locate
|
|
the correct linker and header files.
|
|
|
|
config TOOLCHAIN_HAS_BUILTIN_FFS
|
|
bool
|
|
default y if !(64BIT && RISCV)
|
|
help
|
|
Hidden option to signal that toolchain has __builtin_ffs*().
|