arch_cpu_start() published the boot parameters through
sys_cache_data_flush_range(), which returns -ENOTSUP when cache
management or d-cache support is disabled. The return value was
discarded, so a secondary core could observe stale parameters.
The AArch32 MMU setup enabled the data cache unconditionally, even
with CONFIG_DCACHE disabled, so sys_cache_data_flush_range() could
silently skip the clean while the cache was live. Gate the SCTLR.C
bit in z_arm_mmu_init() on CONFIG_DCACHE, like soc_reset_hook() in
soc/arm/fvp_aemv8r/aarch32/soc.c already does, so that CONFIG_DCACHE=n
does not enable the data cache.
Call arch_dcache_flush_range() and check its result before releasing
the secondary core, and build cache.c for CONFIG_ARCH_CACHE or
CONFIG_DCACHE so the operation exists without cache management. The
flush is then only needed, and only compiled, when CONFIG_DCACHE is
enabled.
Keep the existing dsync barriers; they remain the ordering point when
the flush is compiled out. Include zephyr/arch/cache.h directly
because zephyr/cache.h only exposes the arch cache interface when a
cache type is selected.
This only avoids setting SCTLR.C; a C bit left set by an earlier boot
stage is not cleared.
Fixes#119663
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
d52d4583f5