During arch_cohere_stacks(), the used portion of the outgoing
thread is cache flushed, and then the unused portion of cache
invalidated. However, this results in the cache line at
the stack pointer being flushed and then invalidated due to
how sys_cache_data_*() operates. If we are swapping back to
the same thread (e.g. after handling interrupt), this cache
line will need to be retrieved again from main memory since
it has already been invalidated. This creates unnecessary
data move between cache and main memory. So create our own
version of cache flushing and invalidation routines just for
arch_cohere_stacks(). Bouns is that these work directly with
bounding addresses and skips the size calculation which should
save a little bit amount of execution time.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes _xstack_call1_* trampoline as we can simply use
callx4 to jump to the interrupt handler.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Before cross stack call is setup correctly, we cannot allow
interrupts to be triggered or it may interfere with register
window spilling since we are clobbering registers needed for
that to work. However, there was a brief period where higher
level interrupts could fire due to code writing to PS with
lowered interrupt mask before raising it again. So rework
that part to avoid writing PS with intermediate value, and
now we mask interrupt until everything is setup correctly
before interrupt is enabled again.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When initializing the stack at thread creation, we should not
set the pointer to privileged stack pointer yet as the thread
can be a kernel thread. Only when a thread is transitioning to
user mode, then we need to set the pointer to point to
the privileged stack. This is a purely semantic change and
should not affect any functionality.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the calculation of the return PC earlier in syscall
entry. There is no need to stash it into BSA, load it, do
the calculation and save it back. We can do the calculation
first and save it in BSA at the same time.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
We should not perform a straight OR operation on INTLEVEL as
we have no idea what existing PS.INTLEVEL is. Also, to avoid
any interferences, we disable interrupts very early during
syscall entrance. So we can remove the OR operation as
PS.INTLEVEL will still have all interrupts masked. Note that
we do not really need to OR PS_WOE into PS as we currently
only support windowed ABI which must have PS_WOE set in PS
anyway.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Syscall entrance makes use of ODD_REG_SAVE but it does not
really need to save FPU registers as it is technically
the same thread and same context. So extract call to
FPU_REG_SAVE to interrupt handling code.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds ODD_REG_RESTORE as a counterpart to ODD_REG_SAVE.
Both the code in interrupt handling and syscall exit have
been refactored to use this new macro.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds two parameters for ODD_REG_SAVE for scratch register
and BSA pointer, thus allowing a bit more flexibility on how
it can be called.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes the call to _xtensa_hifi_save() to save the HiFi
registers during syscalls. During syscall, we are not doing
context switching, and technically it is still the same thread.
There is no need to save HiFi registers.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Xtensa ISA reference manual says to do rsync after wsr to
make sure register is updated before rsr. So do that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove CONFIG_XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP as it is
remnant from early MMU enabling work which is not needed as
the page table code is different from early version where
the PTEVADDR would be the same for all memory domains.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
To avoid misconfigurations a comparision has been added which compares the
amount of reported interrupts from the VIM interrupt controller with the
configured number of interrupts via Kconfig.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
On startup the VIM interrupt controller driver had a sys_read32 call with a
bitmask instead of an address. This has been fixed.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Add support for SPI to cc23x0 SoC. Only controller mode is implemented.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
This patch adds an header file which contains helper macros.
These macros can be used to access some device tree properties.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Replace stall guard retry error log on EAGAIN with enable/disable info log.
Log position, sg result and sg status on each rampstat_work_handler() call.
Treat only negative return values from tmc_spi_write_register() and
tmc_spi_read_register() as an error.
Signed-off-by: Anders Nielsen <anders.nielsen@prevas.dk>
When power cuts during a GC operation, the sector is erased again in the
next reboot cycle and the cycle_cnt of the empty ATE is incremented.
If the same power cut happens 255 times in a row, the empty ATE cycle_cnt
will become equal to the close ATE which causes a memory corruption.
Fix this by checking the close ATE cycle_cnt before incrementing the
empty ATE cycle_cnt.
Fixes: #84874
Signed-off-by: Riadh Ghaddab <rghaddab@baylibre.com>
Do not enable CONFIG_NXP_WIFI_SOFTAP_SUPPORT by default as
that should be let for the user to decide whether the AP
mode is compiled or not.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
__cxa_atexit was originally defined by the IA64 C++ ABI, but it has been
adopted by other C++ implementations since then. This function is already
present in lib/cpp/api/cpp_dtors.c, which is built by default when C++
support is enabled, so we don't need another copy in the MWDT-specific
code.
Signed-off-by: Keith Packard <keithp@keithp.com>
Check the order of constructors, making sure those with a specified
priority are called in numeric order after which those without priority are
called.
Signed-off-by: Keith Packard <keithp@keithp.com>
Handle both of these sections in a single chunk of code instead of
separately. We don't need to use the legacy .ctors ABI as both
the constructors array and startup logic are managed within a single
link result.
This can now also be used with ARC MWDT which had been using the .ctors
sections but with .init_array semantics. For ARC MWDT, we now always
discard .dtors and .fini sections as Zephyr will never cause global
destructors to execute. Stop discarding .eh_frame sections so that
exception handling works as expected.
When building a NATIVE_APPLICATION, we ask the native C library to run all
of the constructors to ensure any non-Zephyr constructors are run before
main is invoked. It might be "nice" to split the constructors so that the
Zephyr constructors were executed by the Zephyr code while the non-Zephyr
ones were executed by the native C library. I think that could be done if
we knew the pathnames of either the Zephyr or non-Zephyr files. That might
make a good future enhancement.
Signed-off-by: Keith Packard <keithp@keithp.com>
The samples/subsys/llext/shell_loader test fails when running as a
twister test on the stm32mp135f_dk/stm32mp135fxx platform, with the
following error:
soc/st/stm32/stm32mp13x/soc.c:46:36:
error: array type has incomplete element type 'struct arm_mmu_region'
46 | static const struct arm_mmu_region mmu_regions[] = {
This commit adds the missing arm_mmu.h include to fix the build issue.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
The samples/subsys/llext/shell_loader test fails when running as a
twister test on the stm32mp135f_dk/stm32mp135fxx platform, with the
following error:
zephyr/include/zephyr/arch/arm/mmu/arm_mmu.h:112:9:
error: unknown type name 'uintptr_t'
This commit adds the necessary includes to define the missing types.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Remove sleeptimer as default soc timer and it should be only
used as soc timer if PM is enabled.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
AXP2101 is MFD device. Zephyr already support the regulator part. This
commit introduces intial support for the charger one.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Remove the source of non-determinism during emulation
by keeping terminal events reproducible between runs.
By using the mechanism of precise pause in Renode emulator
every interaction with terminal happens at the same virtual time
from the perspective of an emulated system, hence makes it independent
of the host. Otherwise the result of a test is susceptible to
the load on the host and robot process keywords' timing.
Renode emulator supports precise pausing when specified sequence of
characters is received on a terminal. Besides that,
char delay parameter is specified to set time interval between
consecutive characters entered in the terminal.
'Start Emulation' keyword is redundant, because 'Wait For'
keywords automatically continue emulation up to the nearest pause
event (e.g. matched pattern on the terminal).
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Removed boards that are not exercised in the CI pipeline, as they are
highly downstream-specific and not relevant to upstream validation.
Signed-off-by: Dipak Shetty <shetty.dipak@gmx.com>
Memory allocations in HAL are using data pool. These operations
are in control plane. Add APIs for allocation/free operations on
control pool.
Signed-off-by: Ravi Dondaputi <ravi.dondaputi@nordicsemi.no>
This patch is used to provide clic(eclic) in 64 bit riscv cpu support,
since in 64 bit riscv cpu, the clic irq table entry is also 64 bit,
so we need to use ld/sd to do irq entry load and store
Signed-off-by: Huaqi Fang <578567190@qq.com>
Add initial support for Renesas RZ/G2LC (r9a07g044c22gbg), a 361-pin
package variant of RZ/G2L
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
For the SAI peripheral, the MCLK signal input/output direction is
independent from the TX or RX bit clocks directions (TCR2[BCD] and
RCR2[BCD]). Introduces mclk-output property.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
