boards: renesas: Add minimal support for Renesas RZ/G2LC-SMARC

Add minimal support for Renesas RZ/G2LC-SMARC

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>

boards/renesas/rzg2lc_smarc/Kconfig.rzg2lc_smarc

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZG2LC_SMARC
+	select SOC_R9A07G044C22GBG

boards/renesas/rzg2lc_smarc/board.cmake

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R9A07G044C22")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/renesas/rzg2lc_smarc/board.yml

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+board:
+  name: rzg2lc_smarc
+  full_name: RZ/G2LC SMARC Evaluation Board Kit
+  vendor: renesas
+  socs:
+  - name: r9a07g044c22gbg

boards/renesas/rzg2lc_smarc/doc/index.rst

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+.. zephyr:board:: rzg2lc_smarc
+
+Overview
+********
+
+The Renesas RZ/G2LC SMARC Evaluation Board Kit (RZ/G2LC-EVKIT) consists of a SMARC v2.1 module board and a carrier board.
+
+* Device: RZ/G2LC R9A07G044C22GBG
+
+  * Cortex-A55 Dual, Cortex-M33
+  * BGA361pin, 13mmSq body, 0.5mm pitch
+
+* SMARC v2.1 Module Board Functions
+
+  * DDR4 SDRAM: 1GB x 1pc
+  * QSPI flash memory: 512Mb x 1pc
+  * eMMC memory: 64GB x 1pc
+  * The microSD card slot is implemented and used as an eSD for boot
+  * 5-output clock oscillator `5P35023 <https://www.renesas.com/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator>`_ implemented
+  * PMIC power supply `RAA215300 <https://www.renesas.com/en/products/power-management/multi-channel-power-management-ics-pmics/raa215300-high-performance-9-channel-pmic-supporting-ddr-memory-built-charger-and-rtc>`_ implemented
+
+* Carrier Board Functions
+
+  * The FFC/FPC connector is mounted as standard for connection to high-speed serial interface for camera module.
+  * The Micro-HDMI connector via DSI/HDMI conversion module is mounted as standard for connection to high-speed serial interface for digital video module.
+  * The Micro-AB receptacle (ch0: USB2.0 OTG) and A receptacle (ch1: USB2.0 Host) are respectively mounted as standard for connection to USB interface.
+  * The RJ45 connector is mounted as standard for software development and evaluation using Ethernet.
+  * The audio codec is mounted as standard for advance development of audio system. The audio jack is implemented for connection to audio interface.
+  * The Micro-AB receptacles are implemented for connection to asynchronous serial port interface.
+  * The microSD card slot and two sockets for PMOD are implemented as an interface for peripheral functions.
+  * For power supply, a mounted USB Type-C receptacle supports the USB PD standard.
+
+Hardware
+********
+
+The Renesas RZ/G2LC MPU documentation can be found at `RZ/G2LC Group Website`_
+
+.. figure:: rzg2lc_block_diagram.webp
+	:width: 600px
+	:align: center
+	:alt: RZ/G2LC group feature
+
+	RZ/G2LC block diagram (Credit: Renesas Electronics Corporation)
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+Applications for the ``rzg2lc_smarc`` board can be built in the usual way as
+documented in :ref:`build_an_application`.
+
+Console
+=======
+
+The UART port for Cortex-M33 System Core can be accessed by connecting `Pmod USBUART <https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/>`_
+to the upper side of ``PMOD 1``.
+
+Debugging
+=========
+
+It is possible to load and execute a Zephyr application binary on
+this board on the Cortex-M33 System Core from
+the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`).
+
+Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzg2lc_smarc/r9a07g044c22gbg/cm33
+   :goals: build debug
+
+Flashing
+========
+
+RZ/G2LC-EVKIT is designed to start different systems on different cores.
+It uses Yocto as the build system to build Linux system and boot loaders
+to run Zephyr on Cortex-M33 with u-boot. The minimal steps are described below.
+
+1. Follow "2.2 Building Images" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to prepare the build environment.
+
+2. At step (4), follow step "2. Download Multi-OS Package" and "3. Add the layer for Multi-OS Package"
+   of "3.2 OpenAMP related stuff Integration for RZ/G2L, RZ/G2LC and RZ/G2UL" of `Release Note for RZ/G Multi-OS Package V2.0.2`_
+   to add the layer for Multi-OS Package.
+
+   .. code-block:: console
+
+      $ cd ~/rzg_vlp_<pkg ver>
+      $ unzip <Multi-OS Dir>/r01an5869ej0202-rzg-multi-os-pkg.zip
+      $ tar zxvf r01an5869ej0202-rzg-multi-os-pkg/meta-rz-features_multi-os_v2.0.2.tar.gz
+      $ bitbake-layers add-layer ../meta-rz-features/meta-rz-multi-os/meta-rzg2l
+
+3. Start the build:
+
+   .. code-block:: console
+
+      $ MACHINE=smarc-rzg2lc bitbake core-image-minimal
+
+   The below necessary artifacts will be located in the build/tmp/deploy/images
+
+   +---------------+------------------------------------------------------+
+   | Artifacts     | File name                                            |
+   +===============+======================================================+
+   | Boot loader   | bl2_bp-smarc-rzg2lc.srec                             |
+   |               |                                                      |
+   |               | fip-smarc-rzg2lc.srec                                |
+   +---------------+------------------------------------------------------+
+   | Flash Writer  | Flash_Writer_SCIF_RZG2LC_SMARC_DDR4_1GB_1PCS.mot     |
+   +---------------+------------------------------------------------------+
+
+4. Follow "4.2 Startup Procedure" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ for power supply and board setting
+   at SCIF download (SW11[1:4] = OFF, ON, OFF, ON) and (SW1[1:2] = ON, OFF)
+
+5. Follow "4.3 Download Flash Writer to RAM" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to download Flash Writer to RAM
+
+6. Follow "4.4 Write the Bootloader" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to write the boot loader
+   to the target board by using Flash Writer.
+
+7. Follow "4.5 Change Back to Normal Boot Mode" with switch setting (SW11[1:4] = OFF, OFF, OFF, ON) and (SW1[1:2] = ON, OFF)
+
+8. Follow "3. Preparing the SD Card" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to write files to the microSD Card
+
+9. Copy zephyr.bin file to microSD card
+
+10. Follow "4.4.2 CM33 Sample Program Invocation with u-boot" from the beginning to step 4 of `Release Note for RZ/G Multi-OS Package V2.0.2`_
+
+11. Execute the commands stated below on the console to start zephyr application with CM33 core.
+    Here, ''N'' stands for the partition number in which you stored zephyr.bin file.
+
+   .. code-block:: console
+
+      Hit any key to stop autoboot: 2
+      => dcache off
+      => mmc dev 1
+      => fatload mmc 1:N 0x00010000 zephyr.bin
+      => fatload mmc 1:N 0x40010000 zephyr.bin
+      => cm33 start_normal 0x00010000 0x40010000
+      => dcache on
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/G2LC Group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg2lc-general-purpose-mcus-dual-core-arm-cortex-a55-12ghz-cpus-and-single-core-arm-cortex-m33-200mhz-cpu
+
+.. _RZG2LC-EVKIT Website:
+  https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg2lc-evkit-evaluation-board-kit-rzg2lc-mpu
+
+.. _SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide:
+   https://www.renesas.com/en/document/gde/smarc-evk-rzg2l-rzg2lc-rzg2ul-linux-start-guide-rev105
+
+.. _Release Note for RZ/G Multi-OS Package V2.0.2:
+   https://www.renesas.com/us/en/document/rln/release-note-rzg-multi-os-package-v202

boards/renesas/rzg2lc_smarc/rzg2lc_smarc-pinctrl.dtsi

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+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ scif0_pins: scif0 {
+		scif0-pinmux {
+			pinmux = <RZG_PINMUX(PORT_38, 0, 1)>, /* TXD */
+				 <RZG_PINMUX(PORT_38, 1, 1)>; /* RXD */
+		};
+	};
+
+	/omit-if-no-ref/ scif1_pins: scif1 {
+		scif1-pinmux {
+			pinmux = <RZG_PINMUX(PORT_40, 0, 1)>, /* TXD */
+				 <RZG_PINMUX(PORT_40, 1, 1)>; /* RXD */
+		};
+	};
+};

boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.dts

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+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <arm/renesas/rz/rzg/r9a07g044c.dtsi>
+#include "rzg2lc_smarc-pinctrl.dtsi"
+
+/ {
+	model = "Renesas RZ/G2LC SMARC";
+	compatible = "renesas,rzg2lc-smarc";
+
+	chosen {
+		zephyr,sram = &ddr;
+		zephyr,console = &scif1;
+		zephyr,shell-uart = &scif1;
+	};
+
+	ddr: memory@60010000 {
+		compatible = "mmio-sram";
+		reg = <0x60010000 DT_SIZE_M(46)>;
+	};
+};
+
+&scif1 {
+	current-speed = <115200>;
+	pinctrl-0 = <&scif1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};

boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.yaml

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+identifier: rzg2lc_smarc/r9a07g044c22gbg/cm33
+name: Cortex-M33 for Renesas RZ/G2LC SMARC
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - uart
+  - gpio

boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33_defconfig

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+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y