Some boards may have less LED child nodes in the DT than the maximum
number of LEDs supported by the chipset. For these boards, the channel
test must skip the missing LEDs when preparing the color buffer and not
exit in error due to missing info.
Also, some boards may have a color mapping that is different from RGB
and this mapping should be used when providing the buffer to
led_set_color().
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
The led identifer should refer to devicetree ordering, not to the index
used by the controller. This way, it will be possible to deactivate
some leds or to reorganize the indexing if necessary.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Some boards may have connected the enable pin of the chipset to a GPIO.
On these boards, it is necessary to configure and set this GPIO before
using the chipset, otherwise the I2C circuitry is disabled.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
The LP50XX family has a specific register to reset the configuration to
default state from any other state. Use this instead of relying on the
manual configuration of registers during startup.
Based on initial work from: Marek Janus <marek.janus@grinn-global.com>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Update compatible property to align it to the updated lp50xx driver.
Based on initial work from: Marek Janus <marek.janus@grinn-global.com>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Add nodes for all new devices supported by the updated lp50xx driver to
get these enabled as part of the build test.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Add support for LP5009, LP5012, LP5018 and LP5024 devices which only
differ by the number of LEDs they can control.
Also, update application sample to run on all these new supported
devices.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Adds the force parameter to the reset command which is now
provided to the callback hook (if enabled).
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This seems to be failing fairly persistently in CI runs. Filed an issue
for having it checked, let's exclude it from the test run until it's
fixed.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Disable SysTick when STIMER is in use and configure
SYS_CLOCK_HW_CYCLES_PER_SEC setting for it.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst support for the system timer peripheral which
can be found in Apollo4 SoCs.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
UART controller present in Ambiq SoCs is mostly compatible with PL011, but
requires some quirks that are implemented in this commit:
- the peripheral needs to be powered on first, via the PWRCTRL core,
- peripheral clock needs to be enabled and configured via the CLKEN/CLKSEL.
registers.
The quirks mechanism was inspired by support for STM32F4 SoC in the
usb_dc_dw driver (fce0b85eca).
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Add definitions for CLKEN/CLKSEL registers, which are used to control
peripheral clock on the variant of the PL011 UART present in Ambiq SoCs.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
UART controllers present on Ambiq SoCs implement a PL011 compatible
interface, with some minor differences that require certain quirks.
To support them a dedicated compatible is needed.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
The registers definitions will be needed when adding vendor-specific quirks
to this driver, so this commits moves them to a dedicated header file.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst pinctrl support for Apollo4 SoCs.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
58408 fixed compilation for GCC >= 13.1. But -dumpversion's output
length depends on compile time configuration. It might only yield the
major version. So use -dumpfullversion instead, which is guaranteed to
always include major, minor and patch version.
Signed-off-by: Jan Henke <Jan.Henke@taujhe.de>
The spi_nor erase op selection was based on the alignment of the end of
the region to be erased. This prevented larger erase operations being
selected in many cases
Closes#60904
Signed-off-by: Joshua Crawford <joshua.crawford@levno.com>
Adds a new I2C shim driver for Intel SoCs. Builds upon the SEDI bare
metal I2C driver in the hal-intel module.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
The sam0 CMCC configure Cortex-M cache controller. However, it is not
clear how the cache management should be performed. It is nor clear if
instructions like SCB_EnableICache can be used. In this case, if cache
management should be made only by CMCC it may require a dedicated
implementation.
Besides above, the CPU_CORTEX_M4 do not define cache by default which
can signal a bad configuration in tree since the SOC_SERIES_SAME54 do
not define which caches should be available.
This force cache controller disable to avoid issues.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current platform initialization do not take in consideration cache
management for historic reasons. This fixes any miss configuration and
allow users to enable/disable caches at board definition. The default
value is cache disabled and the below examples are for SAMV71 which
have both I/D Cache available:
I Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE=n
D Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_ICACHE=n
I/D Cache disabled:
CONFIG_ICACHE=n
CONFIG_DCACHE=n
I/D Cache Enabled:
CONFIG_CACHE_MANAGEMENT=y
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This replace pre kernel initialization by the platform specific
initialization call. The platform specific init will configure
at very beginning the clocks, flash wait states and cache.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Kconfig.series files to normalize copyright date order from
lower to higher and reorder select entries.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Sometimes, channel C may write wrong register to the target device.
This issue occurs when FIFO2 is enabled on channel C. The problem
arises because FIFO2 is shared between channel B and channel C.
FIFO2 will be disabled when data access is completed, at which point
FIFO2 is set to the default configuration for channel B.
The byte counter of FIFO2 may be affected by channel B. There is a
chance that channel C may encounter wrong register being written due
to the FIFO2 byte counter wrong write after channel B's write operation.
The current workaround is that channel C cannot use FIFO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Uses the zcbor decode bulk function instead of manually parsing the
array in the function to reduce duplicated code.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Uses the zcbor decode bulk function instead of manually parsing the
array in the function to reduce duplicated code.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The system still takes both prefixed and unprefixed dt-bindings files,
but let's use zephyr/ prefixed in the examples and documentation.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
There is no need to use SYS_INIT as the HID specific initialisation
can be done in the main before the usb_enable() call.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
It bothered me that most of the log messages started with the first
letter in the message capitalized when this one did not. Fix it!
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
A small Kconfig option change to increase the descriptor pool size as
well as a dts overlay to select which gpdma to test with is needed for
the test case.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
On ACE a seperate, soc specific, interrupt mask needs to be enabled
to unmask the interrupt. Do so for GPDMA.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
