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drivers: serial: pl011: add definitions for CLKEN/CLKSEL registers

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Add definitions for CLKEN/CLKSEL registers, which are used to control
peripheral clock on the variant of the PL011 UART present in Ambiq SoCs.

Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit is contained in:
Maciej Sobkowski 2023-07-03 15:57:17 +02:00 • committed by Carles Cufí
commit a86ee2f2af
1 changed files with 10 additions and 0 deletions
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10
drivers/serial/uart_pl011_registers.h
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@ -105,6 +105,16 @@ volatile struct pl011_regs *const get_uart(const struct device *dev)
#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable */
#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable */
/* PL011 Control Register - vendor-specific fields */
#define PL011_CR_AMBIQ_CLKEN BIT(3) /* clock enable */
#define PL011_CR_AMBIQ_CLKSEL GENMASK(6, 4) /* clock select */
#define PL011_CR_AMBIQ_CLKSEL_NOCLK 0
#define PL011_CR_AMBIQ_CLKSEL_24MHZ 1
#define PL011_CR_AMBIQ_CLKSEL_12MHZ 2
#define PL011_CR_AMBIQ_CLKSEL_6MHZ 3
#define PL011_CR_AMBIQ_CLKSEL_3MHZ 4
#define PL011_CR_AMBIQ_CLKSEL_48MHZ 5
/* PL011 Interrupt Fifo Level Select Register */
#define PL011_IFLS_RXIFLSEL_M GENMASK(5, 3)
#define RXIFLSEL_1_2_FULL 2UL