Add CDC Ethernet Control Model class implementation for the
new experimental USB device support based on the existing
implementation subsys/usb/device/class/netusb/function_ecm.c.
The implementation forms virtual ethernet connection between
USB host and USB device and requires two corresponding MAC
addresses, one for the virtual interface on the device side,
and other for the host which is described by a string descriptor.
With upcoming changes it should also possible to use a real
ethernet controller as media access on the device side.
CDC ECM implementation supports multiple instances which are
specified using DT. The number of instances is limited by the
number of endpoints on the controller, two to three should usually
be possible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add check to see if RPA is already generated for adv sets
with same id. If generated use the same address for all adv sets
with same id else create new RPA.
Signed-off-by: Nithin Ramesh Myliattil <niym@demant.com>
If clock frequency was already high and a ahb prescaler greater than 1
was used frequency could temporary become higher than allowed.
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
Add proper validation check for the number of subgroups
attempted to be added to the broadcast source.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
add dma supported on board nucleo_h743zi.
the twister test is now enable for tests/drivers/adc/adc_dma on board
nucleo_h743zi.
used on driver st_stm32_adc with CONFIG_ADC_STM32_DMA=y.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
add platform_allow nucleo_h743zi.
the twister test is now enable for tests/drivers/adc/adc_dma on board
nucleo_h743zi.
used on driver st_stm32_adc with CONFIG_ADC_STM32_DMA =y.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Update LTDC driver to use LCDIF bindings, to simplify bindings
between LCD interface controller IP blocks.
Boards supporting the LTDC are also updated to use the properties as
declared by the new lcd controller binding
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add common LCD interface binding. This binding captures the
following properties, which are shared between multiple LCD interface
IP blocks:
- VSYNC/HSYNC pulse width
- Vertical/Horizontal front and back porch
- HSYNC,VSYNC,data enable, and pixel clock polarity flags
- pixel clock frequency
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds the "area: Coding Guidelines" label to the "Coding
Guidelines" area.
Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
This commit adds more coding guidelines and code style-related files to
the "Coding Guidelines" area; most importantly, it adds the coding
guidelines document itself (`doc/contribute/coding_guidelines/`) to the
area.
Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
Add the alias to the MX25LM512 octo-NOR flash for the spi-flash node.
Remove the overlay for the samples/drivers/spi_flash as no MDMA driver
exists yet for the stm32h7.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update Zephyr fork of MCUboot to revision:
2878eb4e32fabc14bc391c3221cbf285064d9db4
Brings following Zephyr relevant fixes:
- ec2ac82c boot/zephyr: switch main return type to 'int'
- 67693442 boot: zephyr: esp32: zephyr port
- 0a1ef372 bootutil/crypto: Move BOOTUTIL_CRYPTO_ECDSA_P256_HASH_SIZE
into common
- 10529d30 bootutil/crypto: Have a single ECDSA verification module
- 966ac818 bootutil/crypto: Extend ECDSA to support P384 curve
- 25390ad5 bootutil/crypto: Have a single ECDSA abstraction file
- cf36d670 bootutil/crypto: Add license disclaimer to ecdsa_p256.h
- 557451d2 bootutil/crypto: Add a generic signature validation module
for ECDSA
- c725cee1 docs: Add release note snippet for ECDSA TLV
- 30978516 sim: Remove curve specific ECDSA TLVs
- 6205c10f sim: Add generic ECDSA TLV support
- 5704174c imgtool: Add generic ECDSA TLV support
- b08e77e0 bootutil: Create new generic ECDSA TLV
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The page tables test checks to make sure the various page permissions are
set as expected, but when there's a malloc heap, things don't match the
test expectations. As this test doesn't require a heap, just disable it.
Signed-off-by: Keith Packard <keithp@keithp.com>
Instead of detecting that the minimal C library is in use before running
the malloc failure tests, check for the common malloc being in use as that
will also allow this test to run with picolibc.
Signed-off-by: Keith Packard <keithp@keithp.com>
The malloc arena needs to be aligned to a suitable size on Risc-V, and the
Z_RISCV_STACK_GUARD_SIZE variable is a helpful proxy for what size that
is. However, that is not always a power of two, so round it up to make the
linker capable of performing the necessary allocation.
Signed-off-by: Keith Packard <keithp@keithp.com>
This function may be used by system libraries (like libstdc++), so instead
of gating compile on target language, always build this function and gate
API visibility in header files instead.
Signed-off-by: Keith Packard <keithp@keithp.com>
Not all xtensa targets define the top of usable RAM via the _heap_sentry
address; it looks like the list is limited to esp32, esp32s2, esp32s3 and
intel parts. The first three all define HAS_ESPRESSIF_HAL, so key the test
using that or SOC_FAMILY_INTEL_ADSP.
Signed-off-by: Keith Packard <keithp@keithp.com>
Instead of explicitly initializing the mutex at runtime, use
SYS_MUTEX_DEFINE to initialize it at build time instead.
Signed-off-by: Keith Packard <keithp@keithp.com>
This sample application demonstrates the implementation of an
MQTT client that can publish messages to AWS IoT Core using
the MQTT protocol.
Fixes#22866
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
Intel ISH SoC can't reboot via RST_CNT register,
so make sys_arch_reboot as weak function to allow
implement different arch reboot in SoC layer.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
Move definitions of the STM32 FDCAN specific registers to the front-end
driver implementation and implement remapping of these registers to/from
the standard Bosch M_CAN registers.
Some of the STM32 FDCAN register bit fields are limited in size compared to
the Bosch M_CAN specification. This is due to hardware limitations on the
number of elements in the various sections of the Message RAM. Add build
assertions to ensure the number of elements specified do not exceed the
hardware limitations instead of using custom definitions for these fields.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move definition of the NXP LPC MCAN specific Message RAM Base Address
register (MRBA) to the front-end driver implementation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Some Bosch M_CAN IP core implementations use a fixed Message RAM
configuration, other use a fixed memory area and relative addressing,
others again have custom registers for configuring the Message RAM.
Move the responsibility for configuring the various Bosch M_CAN Message RAM
addresses to the front-end drivers. This removes some of the front-end
specific code from the backend. Provide a helper function for configuring
the most common variations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Expose the can_mcan_read_reg()/can_mcan_write_reg() along with all the
Bosch M_CAN register definitions for use in Bosch M_CAN driver front-ends.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Let the Bosch M_CAN front-end drivers supply their own register read/write
functions.
This is preparation for handling non-standard Bosch M_CAN register layouts
directly in the front-end and for accessing Bosch M_CAN IP cores over
peripheral busses.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Use sys_read32()/sys_write32() instead of volatile struct for register
access. Be consistent in using unsigned constants in register
comparisons. Use locking around register read-modify-write operations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
When the optional env_suffix_${env_var} was not set, USER_CACHE_DIR was
slightly malformed and had double slashes,
e.g. /home/user/.cache//zephyr.
To fix it string(JOIN ...) is used, which only sets slashes when
necessary.
Signed-off-by: Manoel Brunnen <mb@lee-brunnen.de>
Implement profile-agnostic broadcast source and broadcast
stream structs, similar to the unicast stream struct.
The purpose of these are to be able to use the same structs
for multiple profiles such as BAP, CAP and TMAP.
Since only the BAP shell implements broadcast support at this
moment, the changes are minimal, but makes it easier to implement
broadcast support for other profile shells.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Add DT overlay to be able to support and test usb_dc_dw driver
(snps,dwc2) on nucleo_f413zh board. This disables STM32 shim
driver described and configured on the SoC and board level.
Obviously,it works with other STM32F4 boards as well, but we
do not have a mechanism to apply it generically yet, upcoming
snippet support may fix that. Until then, we need something for
development and as an example.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Currently, the usb_dc_dw driver is not enabled for any platform.
Allow to build the driver for cyclonev_socdk. Subsequent patches
will allow the driver to be used on additional platforms.
Enable USB device controller and use use new snps,dwc2 compatible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This commit is a draft to support more controller implementations
with these drivers. The goal is also to make it easier to port
this driver to the new UDC API later.
We use compatible, like st,stm24f4-fsotg to support and enable
vendor-specific quirk. The core of the driver remains generic,
and therefore described and enabled by snps,dwc2 compatible.
STM32F4 support requires PINCTRL, even though pinctrl API is
generic, not all platforms implement it, so we have to include
and compile it conditionally.
Now we also switch to use new snps,dwc2 compatible and
explicitly force the controller into device mode,
as we do not support other roles or role changes.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add definition for GHWCFG1..4 registers to be able to obtain basic
information about PHY, endpoints, and Data FIFO.
Add GGPIO defines for STM32F4 SoC family USB controllers.
This implementation uses GGPIO to enable transceiver, VBUS
detection, and a few other functions.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Although snps,designware-usb bindings already exist, this one is
prolematic. Compatible is too general and does not reflect
the actual controller IP. It has Zephyr-specific properties,
but has no zephyr prefix. It forces properties that are not
necessary for this controller. We start here with new bare minimum
properties for DesignWare OTG USB 2.0 controller.
The STM32F4 SoC family USB controllers, which are also implement
DesignWare OTG USB 2.0 IP, can also be used with existing drivers,
but require certain quirks. To use these we need special compatible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Align and sort defines according to the position in memory.
Remove unnecessary parentheses.
Fix USB_DW_DSTS_ENUM_SPD_MASK.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Cleanup includes, fix build and missing kernel header include.
Move copyright notice to the top.
USB_DW_* macros are a bit misplaced in register header,
which is supposed to be about registers only.
USB_DW macro is used to point to base of controller register set.
Move it to driver code and add a new variable in driver's configuration
that takes the base address of the instance. This also makes later
porting to UDC API and support multiple instances easier.
Remove redundant DW_USB_IN_EP_NUM and DW_USB_OUT_EP_NUM
macros. Do not limit number of endpoint register in
struct usb_dw_in_ep_reg as it does not reflect common
register mapping of the controller.
Fix build warnings caused by USB_DW_EP_FIFO and use base variable
to calculate data FIFO access register.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
In the case that there is a situation where the controller
oscillator start-up timer doesn't expire, or the SPI can't
read the CLKRDY bit the driver would hang during init.
The config option ETH_ENC28J60_CLKRDY_INIT_WAIT_MS sets
the time that the driver will wait for OST before returning
an ETIMEDOUT error.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
