This adds a new kconfig CONFIG_SRAM_OFFSET to specify the offset
from beginning of SRAM where the kernel begins. On x86 and
PC compatible platforms, the first 1MB of RAM is reserved and
Zephyr should not link anything there. However, this 1MB still
needs to be mapped by the MMU to access various platform related
information. CONFIG_SRAM_OFFSET serves similar function as
CONFIG_KERNEL_VM_OFFSET and is needed for proper phys/virt
address translations.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Z_BOOT_VIRT_TO_PHYS() and Z_BOOT_PHYS_TO_VIRT() address
translation macros are flipped in their calculations.
The calculation is supposed to be:
virt = phys + ((KERNEL_VM_BASE + KERNEL_VM_OFFSET) -
SRAM_BASE_ADDRESS)
So fix the them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit fixes some edge cases when using net_bufs with reserved
bytes (headroom) as fragments of a net_pkt.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
net_buf_max_len() provides the maximum number of bytes which can be put
behind the data pointer. This provides a save alternative to using the
size field of the net_buf structure directly, which does not take the
reserved bytes (headroom) into account.
This commit also replaces the usage of the size field in places where
size got used directly. Code has not been adjusted when it is easy to
recognise that the buffer does not have any reserved bytes, which is the
case after allocation or reset. Same goes for the faulty usage by
net_pkt as exposed by the last commit and begin fixed by a separate
commit.
Even though it would be cleaner, I decided to not rename the size field
to e.g. __buf_size in order to keep the amount of code changes low.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
When operating on a net_pkt using the cursor functionality, reserved
bytes (headroom) are currently not respected.
This commit adds test cases exposing this problem. Fix will be
introduced in a later commit.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
The ASSERT order is backwards, where the shell->ctx is being accessed
before it is being checked as valid. Moving the check for the
shell->ctx to before the using it.
Signed-off-by: Dan Kalowsky <dkalowsky@amperecomputing.com>
Absolute timeouts were covered, but nothing was testing their actual
expiration time and there was an off-by-one.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The computation was using the already-adjusted input value that
assumed relative timeouts and not the actual argument the user passed.
Absolute timeouts were consistently waking up one tick early.
Fixes#32499
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Instead of doing these in assembly, use the common z_bss_zero()
and z_data_copy() C functions instead. This simplifies code
a bit and we won't miss any additions to these two functions
(if any) under x86 in the future (as x86_64 was actually not
clearing gcov bss area).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves calling z_loapic_enable() from crt0.S into
z_x86_prep_c(). This is done so we can move BSS clearing
and data section copying inside z_x86_prep_c() as
these are needed before calling z_loapic_enable().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The stm32 uart driver fails to build on certian platforms due to
changes introduced by:
commit 3c18bcbf77
Author: Francois Ramu <francois.ramu@st.com>
Date: Wed Jan 27 10:27:33 2021 +0100
drivers: serial: stm32 restore uart after lowpower
Fix this by adding some ifdef's around the code that is specific to the
given platforms that the code works on.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Current implementation of uart_npcx_irq_{tx,rx}_ready always returns
false if the respective interrupt enable bit is not set, which means
that the api cannot be used if the interrupts are temporarily disabled
for whatever reasons, breaking patterns such as [1].
Other uart drivers also seems to not have this check, this patch removes
it from the NPCX driver too.
[1] https://github.com/zephyrproject-rtos/zephyr/blob/master/drivers/console/uart_console.c#L549
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Now that we have consolidated tf-m signing, the combined
binary is always named tfm_merged, so we need to modify
the QEMU targets in the tfm-integration samples.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Place the new signing code in the TFM module CMakeLists.txt.
Make some small tweaks and add a sentence to the docs.
In the process, make a few changes to the signing code:
- Change some names of files created.
- Minimize the number of files created.
- Use hex files instead of bin files. This is so we don't need to know
the offset when creating hex files from bin files.
Also add signing for MCUBOOT_IMAGE_NUMBER=1 based on the code from the
v2m_musca_b1 board, though, this board does not build with =1 now
because of (I assume) some flash aliasing which places the S and NS
images 0x10000000 apart, where the manual algorithm places them next to
each other. It builds with =2, though.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Besides implementing a customized pm_policy_next_state() in the
application layer, a customized device policy handler of power
management, pm_policy_low_power_devices(), is also needed if
CONFIG_PM_POLICY_APP is enabled. This CL adds this function to prevent
build errors.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Since the uart device clock will be stopped after ec entered sleep or
deep sleep state and restore its clock automatically, there is no need
to implement code for suspending and resuming devices manually.
The driver still needs to check the current status of uart device when
it wants to change its power state to LOW or SUSPEND power state. It is
crucial to forbid ec enters sleep or deep sleep state when uart device
is busy with transmitting data. Or we will observe broken characters on
the uart console.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This will export the stm32_clock_control_init function
to restore the clocks after the low power modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
stm32wb and stm32l4 are devices which supports the low power
from the Kernel PM, so is the PM_DEVICE defined.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the policy is not available or defined by th application
the pm_policy_low_power_devices is still valid
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The clock configuration is restored by the stm32_clock_control_init
function of the clock_stm32_ll_common driver
when exiting the low power mode
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the policy is not available or defined by th application
the pm_policy_low_power_devices is still valid
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The clock configuration is restored by the stm32_clock_control_init
function of the clock_stm32_ll_common driver
when exiting the low power mode.
Keeping the stm32wbxx_ll_utils.h in case the PLL is used for wb.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds qemu_x86_lakemont to the platform allow list
for the FPU sharing tests. Since Lakemont supports SSE3
and SSSE3, it is better to test them also.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
