An additional devicetree poperty `single-wire` is added
to uart and usart bindings of stm32. The driver checks this value
during initialization and enables the single wire mode when set.
Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
Use pm_state_cpu_get_all to obtain CPU states instead of using extra ROM
duplicating existing information already holded by the PM subsystem.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The Event FIFO start address (EFSA) field within the Tx event FIFO
configuration register (TXEFC) occupies bit 15:2.
Change the CAN_MCAN_TXEFC_EFSA_POS definition to reflect this.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Rename a few CAN API functions for clarity and consistency with other
Zephyr RTOS APIs.
CAN_DEFINE_MSGQ() becomes CAN_MSGQ_DEFINE() to match K_MSGQ_DEFINE().
can_attach_isr() becomes can_add_rx_filter() since a filter callback
function is not an interrupt service routine (although it is called in
isr context). The word "attach" is replaced with "add" since filters are
added, not attached. This matches the terminology used is other Zephyr
APIs better.
can_detach() becomes can_remove_rx_filter() to pair with
can_add_rx_filter().
can_attach_msgq() becomes can_add_rx_filter_msgq() and documentation is
updated to mention its relationship with can_add_rx_filter().
can_register_state_change_isr() becomes can_set_state_change_callback()
since a state change callback function is not an interrupt service
routine (although it is called in isr context). The word "register" is
replaced with "set" since only one state change callback can be in
place.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This patch controls the SPI of the stm32H7 mcu when using
the DMA transfer. Starting and ending the transfer
are specific according to the RefMan.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
A generic function is used to give the register address to the DMA.
The SPI of the stm32H7 serie has two data registers for Tx and Rx
When the DMA is getting the address it differs between Rx and Tx.
As the stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_spi.h
has no such LL functions, the register address is get direclty.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The spi_stm32_complete() is checking spi flags which are valid when the
intance is still enable: disable afterwards. No more need to disable
the DMA transfer then
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Defines a function to control the spi busy state during DMA transfer.
After the DMA Tx, the spi might still have some data to Transmit.
The driver must wait for the SPI Tx before sending the next packet.
This is not required for the Rx part as the DMA Rx is already done.
Some mcus like stm32H7 have a TX complete bit, other must wait for the
TXE and BSY line.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Initial version of a PWM driver for GigaDevice GD32 SoCs. Only PWM
output is supported for now (no capture support).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold
detectors from offset 0x14 & has 10 input channels. NPCX9 has 6
threshold detectors from offset 0x60 & has 12 input channels.
This commit fixes the NPCX ADC register structure.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Theoretically, source id check is not mandatory in the context we use
VT-D here (i.e. non VM one, just multi-vector MSI support)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Not sure this is requered as we do not mangle with domains, but let's
make sure this cache is clear.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
A surprising issue: while sys_set_bit() on VTD_GCMD_REG work on
apollo_lake, it seems to create border effect on elkhart_lake: it may
reset some previous bit to 0.
So switching to full write of the register at once, which works for
both.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
VT-D will only be enabled if MSI multi-vector will also be requested,
on x86_64, for all boards BUT QEMU ones.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no point to enable VT-D if PCIE MSI multi-vector support is not
requested, as VT-D is uniquely being used to remap MSI multi-vector
based interrupts.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Those MMIO registers might be mapped in RAM and thus it's
really important to keep storage space for such mapping.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
QI operation are not supposed to last forever.
It's not an actual timeout based on clock, but a dummy counter instead.
That's because system clock might not have beed initialized yet, since
VT-D's init comes first (and that same init will use QI...)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Depending on a VT-D capability, it might be necessary to flush objects
from the cache.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Looks like it's mandatory to invalidate the Interrupt Entry Cache in
VT-D and the only way to do so is to enable Queued Interface.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
IR faults are non-recoverable, so it's good to know why. Thus let's
handle the fault event and print the fault.
Other faults are printed as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Looks like a source of fault if pieces of IRTE are written instead of
the whole 64 bits block it belongs to.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
If VT-D's interrupt remapping is in place, all IOAPIC RTEs need to get
remapped as well (or then they will be simply blocked).
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Adding a way to pre-install the irg/vector on an irte and a way to get
an irte based on irq/vector.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will not only be used by MSI remapping but by all relevant
interrupts.
Fix also IRTE settings:
- handle x2apic for destination id
- destination mode is always logical (as for IOAPIC)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
In XAPIC mode, it's possible to tell VT-D to let interrupt in compatible
format passing through.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
SHV bit depends on the number of vectors allocated.
If it's facing a multi-vector MSI array, it will set the bit.
If not the bit must be 0.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Refactor to handle this case. This is valid only when MSI multi-vector
feature is enabled.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The is meant to fix a chicken & egg issue with MSI interrupt remapping.
Currently, drivers first connect the irq (by-passing any possible MSI
remapping), so the IRQ ends-up being remapped at the IOAPIC level which
is not what we want.
So adding a dedicated function to properly handle this case. This is
valid only for runtime dynamic IRQ connection obviously.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
And since it does yet another round of pcie_get_cap() on PCIE_MSI_CAP_ID
and PCIE_MSIX_CAP_ID, let's factorize that into a utility function and
change the relevant places to use that function instead.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The host reassembles fragmented advertising reports from the controller.
Non-complete advertising reports from different advertisers may not be
interleaved. If non-complete advertising reports from an advertiser
is received while advertising reports from another advertiser is
reassembled, an error message is logged and the advertising report is
discarded. Future scan results may be incomplete.
Advertising reports from legacy PDUs or complete extended advertising
reports may be interleaved as these do not require reassembly.
If the controller sends more advertising data than fits in the
reassembly buffer, the data is truncated. Further advertising reports
from the advertiser are discarded until the final complete advertising
report is received and discarded.
Signed-off-by: Herman Berget <herman.berget@nordicsemi.no>
Enable the emulated GPIO driver by default if instances exist in
devicetree. This removes the need to manually enable `CONFIG_GPIO_EMUL`
when `CONFIG_GPIO` is enabled.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
General refactoring to clean up and futureproof this driver.
Remove false dependency on CONFIG_CAVS_ICTL. This requires the CAVS
interrupt mask API, but doesn't touch the interrupt controller driver.
Remove a racy check for simultaneous interrupts. This seems to have
been well intentioned, but it's needless: the spinlock around the
last_count computation guarantees that colliding interrupts will
correctly compute elapsed ticks (i.e. the last will compute and
announce zero ticks, which is correct and expected). And this opened
a tiny window where you could incorrectly ignore a just-set timeout.
Factor out the specific registers used (there are only five) into
pointer-valued macros instead of banging them directly.
Unify interrupt initialization for main and auxiliary cores.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Instead of using maskstatus to see if an interrupt has fired,
use finalstatus instead. It has been observed that some
controllers do not update maskstatus correctly with incoming
interrupts, but finalstatus works fine.
FYI, the DW driver in Linux is also using finalstatus.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Recent changes in this function made the code now compatible
with the use of LL API to perform this configuration.
Use it to simplify the driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fix hard fault due to NULL being passed as argument into
rssi_handler, which now derives the gsm_modem struct pointer from
the argument.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
