Disabling clock may conflict with concurrent usage of GPIOs and pins in
AF mode. This can be improved once a proper clock control API is in
place.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add GPIO driver for Gigadevice SoCs. The driver supports devices with
the AF and AFIO models.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add initial support for the GigaDevice External Interrupt Controller.
This driver is required to manage GPIO interrupts. Only EXTI lines 0 to
15 are supported for now (no LVD, RTC, etc.). Driver can be extended in
the future to add support for extra EXTI lines.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This change provides support for 4 IO read (via 4READ command) and
program (via 4PP). Flash memory pins SIO[0123], CLK and CS are used.
All of them are controlled by stm32 QSPI IP block.
The instruction code for fast reading as well as number of latency
cycles required are read from SFDP structure provided by flash memory.
The number of required read latency cycles when performing reading
is the sum of SPI-NOR memory mode bits and wait states (also named
as 'dummy cycles').
It also has been assumed that memory, which supports fast read (4READ),
also will support fast programming (4PP command) as this information is
not available in SFDP.
One also need to enable the QUAD IO support in board's device tree by
defining 'spi-bus-width = <4>' property. It is required as it may
happen that not all QSPI dedicated pins are used (for example only two
of them are available).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
For proper operation of QUADSPI IP block, both sides of communication;
NOR flash memory and STM32 controller need to support 4 IO
transmission.
After this change the QSPI stm32 driver is able to program NOR flash
memory to switch itself to use all 4 IO lines (SIO[0123]) to transmit
and receive data.
The QE bit (in SPI-NOR's Status Register) is the non-volatile one, so
setting it is done only once (at first boot of the device).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit provides define for reading the control register (CR) on
the flash memory.
In that register the information about 4B addressing is stored.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Some flash memories connected to QUADSPI IP block on stm32[fh]7 devices
require proper reset pulse before configuration.
This patch adds two new properties - the 'reset-gpios' phandle,
which allows specifying GPIO pin for RESETn pulse and
'reset-gpios-duration', which provides the time (in ms) for reset
duration.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The 'flash-id' property defines the number of QSPI's dedicated GPIO
bank (and flash ID), which will be used to communicate with flash
memory.
For example, on stm32h7xx it is possible to use 'quadspi_bk1_*' and
'quadspi_bk2_*' set of pins, so one may need to select between them
when required.
By default - pins from 'quadspi_bk1_*' bank are used, so the
'flash-id = <2>;' property, when your use case (e.g. PCB design)
requires it, forces usage of 'quadspi_bk2_*' pins.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The stm32 HAL code for qspi (SHA1: 5c8275071ec1cf160bfe8c18bbd93):
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_qspi.c implicitly
depends on the stm32h7xx_hal_mdma.c driver as it uses unconditionally
'HAL_MDMA_Abort_IT()' function.
To avoid build breaks - no matter if QSPI IP block works with DMA
or interrupts - the CONFIG_USE_STM32_HAL_MDMA shall be defined.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In npcx_itim_evt_isr, it updates the cyc_sys_announced variable and
then calls sys_clock_announce() to update the kernel curr_tick variable.
If an ISR handler with higher priority preempts the timer ISR after the
sys_clock_announce is updated and before the sys_clock_announce() is
called, it will read the wrong time when calling k_uptime_get() because
the cyc_sys_announced and the curr_tick are not synchronized.
The commit fixes the problem by raising the timer's interrupt priority
to the highest one (i.e. 1 in npcx's configuration).
This commit also moves the computation of the delta cycle inside the
spinlock in sys_clock_elapsed() to prevent another potential racing
condition.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Convert the CAN loopback driver from being configured via Kconfig to
multi-instance configured via devicetree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
gsm_ppp_stop should cancel possible running work items.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
The 'work' argument of a delayable work's handler should be
converted to delayable work before passing into the CONTAINER_OF
macro.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This commit introduces the following changes:
* nrf_rtc_timer is extended with a capability to handle RTC overflow,
allowing it to operate on absolute RTC ticks, rather than relative
ticks.
* overflow handling is ZLI-proof and relies on the sys clock
handler being executed twice every RTC counter's overflow.
* callbacks are given an absolute RTC tick value as a parameter instead
of CC register's value. The absolute RTC tick value is the RTC counter
value set during CC channel configuration extended to 64 bits.
* in case the timer's target time is in the past or is the current tick,
the timer fires as soon as possible, however still from the RTC's ISR
context.
* in case an active timer is set again with the same target time, it is
not scheduled again - only its event data is updated. Otherwise, the
timer is scheduled as usual.
* a scheduled timer can be aborted.
* system clock functions are now using 64 bit values internally.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Signed-off-by: Paweł Kwiek <pawel.kwiek@nordicsemi.no>
ESP32 uart_poll_in should return 0 on success and not
the total amount of data read.
This also adds a check in fifo_fill call to
avoid negative values, otherwise it would send garbage
to uart
Closes#41352
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Don't re-enable the DIO1 interrupt when the modem is in sleep mode. This
fixes the power regression introduced in Zephyr v2.7.0 #41026.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The msg_sram resides in the sram region, where the
m_can controller direcly access it. Whenever the driver
writes to the msg_sram and operations are triggered, the
cache needs to be invalidated.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
RM 0453: the sw is allowed to write the Oversampling
ratio or shift of the ADC Config.Reg.2 only when ADSTART = 0
(no conversion is on-going). So disabling it will be stopped.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
RM 0453: the sw is allowed to write the Data Resolution bits
of the ADC Config.Reg.1 only when ADEN = 0 (ADC disable).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a dummy driver for the `vnd,gpio` compatible to allow compilation of
drivers utilising GPIO when running "build_all" tests.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This commit adds the API of page_layout that will make test of
test/drivers/flash pass on it8xxx2_evb board.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change the can_tx_callback_t function signature to use an "int" (not an
uint32_t) for representing transmission errors.
The "error" callback function parameter is functionally equivalent to
the return value from can_send() and thus needs to use the same data
type and needs to be able to hold negative errno values.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The driver performs AT commands configurations using the
system workqueue, this can delay the workqueue by up to 6
seconds to wait for the modem replies, which isn't ideal.
This PR creates a dedicated workqueue for the gsm, and
provides a helper function to reschedule work items to the
gsm workqueue.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
STOP command was issued in the same transmission message
and as from esp-idf, this should be moved into a new
transmission.
Although it works in most scenarios, SHT3X sensor is one
case that presents reading error.
Closes#41385
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The PINCTRL_DT_(INST_)DEFINE macros already defined the trailing ;,
making its usage inconsistent with other macros such as
DEVICE_DT_DEFINE.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
PR #38482 made the sam0 i2c send NACK when receiving a single message
Fixes#38878Fixes#41016
Signed-off-by: Christoffer Zakrisson <rustypig91@gmail.com>
SYS_INIT can be used for the same purpose, what is being run is simply
an initialization hook.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
If there are no console messages input at an interval of 15
seconds, the system will be able to enter suspend mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add length checks before calls to net_buf_add_mem
for dynamically sized data.
This should give a better error response than hitting
the __ASSERT in net_buf_simple_add.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
some build error due to adding rt11xx support without testing
update mclk enable to avoid add pinmux driver
note:
some other PRs still in progress to full enable i2s on rt platform
this fixing: #41153
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Specify in the API that the callback must be registered before the
channel is enabled, fix the NRFX IPC driver to be compliant and change
the MBOX sample.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Fix a problem introduced in 6ea54db334 that caused the poll operation to
take 10x more time than intended.
Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
MCHP ADC configuration register need to be updated with appropriate
clock time values for high & low time clock.
Signed-off-by: Aditya Bhutada <aditya.bhutada@intel.com>
Deprecate the can_attach_workq() API call.
This API is limited in its functionality (it does not work with
userspace, it uses one common buffer size for all work queue instances).
Similar functionality can easily be implemented using the
can_attach_msgq() API along with the generic triggered work API
(e.g. using k_work_poll_submit()).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Convert the CAN shell from using can_attach_workq() to using
can_attach_msgq() and triggered work via k_work_poll_submit().
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Driver was not behaving according to API description and
was not returning -EBUSY when uart_rx_enable() was called
on already enabled receiver.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This is a follow-up to commit 4dfab40cac.
The calculation of the pixel period is done incorrectly and results
in higher than configured refresh frequency if pixels are refreshed
in groups. Fix that and lower the base frequency for the timer and
PWM so that wider range of refresh frequency can be used also with
the pixel grouping.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Sending AT+CWLAP was introduced with commit f2859f9501 ("drivers:
wifi: esp_at: changes to scanning") as a way to easily test introduced
changes, rather than on purpose. Remove that now, as there is no
particular reason to send it and additionally it breaks setup phase:
<err> modem_cmd_handler: command AT+CWLAP ret:-5
<err> wifi_esp_at: Init failed -5
with ESP-AT firmware v2.1.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
PCIE now uses the new interface. And pcie_alloc_irq() is only made
available when CONFIG_PCIE_CONTROLLER is unset. So only for x86 atm.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
i2c_burst_write can have portability issues with certain i2c
peripherals that can fail when this api is called. This fixes the case
where this can be easily replaced with i2c_write in mcp230xx,
pca95xx, stmpe1600, max17055, and tmp112.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
So far driver was using SENSE mechanism for all or none edge
interrupts. This was not convenient since in some modules may
require IN event to be used and other did not. Converting it to
use a mask specified in the device tree. Pins indicated in the
mask will use sensing.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add a new DT property named "pixel-group-size" that allows users to
configure the driver to refresh the matrix by illuminating multiple
LEDs in particular rows simultaneously. This way the maximum possible
brightness of the LEDs can be increased (as they can be lit longer)
and the timer interrupt handler is executed less frequently, what
results in decreased CPU load, but more GPIOTE/PPI channels needs to
be allocated if the PWM peripheral cannot be used. Thus, it is left
to users to select the configuration that suits them best.
Update definitions of both the bbc_microbit boards with this new
property, using the maximum available group size (to achieve maximum
possible brightness). For v2, no new resources are used (only all
channels in the already used PWM peripheral are now utilized).
For v1, two more GPIOTE and PPI channels are allocated.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fix pin disconnection when COFNIG_PINCTRL=n, so that less power is used
in suspended state. This seems to be a copy-paste kind of bug, since
when both resuming and suspending the same configuration was applied.
Fixes: 5567d7ae07 ("drivers: serial: nrfx_uart: add support for
pinctrl")
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Some STM32 series need to configure health test register
for proper RNG behavior.
In addition, some also require to write a Magic number
before writing the configuration.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Rework bbc:microbit display support to use nRF LED matrix
display controller driver and allow to use it with
bbc:microbit v2 board.
This patch turns the driver into a higher level driver
using the display controller API. Code that directly
accesses hardware (GPIO) is removed.
This driver is reworked to be more generic. It still
has a lot of potential for improvement, but it requires
changes in all applications that use this tool.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
