The name change for cavstool.py has also broken the backward
compatibility for SOF testing. Rename cavstool_server.py back
to cavstool.py. Keep the functionality still as same as the previous
one.
And also update the documentation of it.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
The new client-server-based cavstool has broken the SOF CI testing
due to not considering that loading firmware and output log directly
without daemon is still necessary. Fix that when it is not running
as a daemon.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The soc.c source file did nothing, so just remove it. Remove soc
directory from the include list as well, since there's no header in the
directory that needs to be exposed to the Zephyr build.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Note that in this case, none of the definitions are used in-tree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
In this case, the file did not use anything defined in <soc.h>, it only
required access to integer types, e.g. uint32_t.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
SOCFPGA_SYSMGR_REG_BASE is the only definition from soc.h used in tree,
move it to the file using it. Note that this looks suspicious: base
address should come from Devicetree. This patch will allow to drop
soc.h.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
arch/cpu.h was not needed, devicetree.h and sys/util.h are required for
DT API and ARRAY_SIZE().
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add a new selectable Kconfig option to decide wether the device driver
is a MMIO device or not. Previous to this patch, the decision was maded
based on the existence of a definition in <soc.h>. The design was
fragile, as code compiled anyway if the definition was not present.
All platforms/boards that had the definition in <soc.h> select the
Kconfig option in their respective defconfig files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Aspeed AST10x0 series SOC has a SYSCON hardware block at address
0x7e6e2000. Enable this option to enable relative driver.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
This patch is doing several things:
- Core ISA and extension Kconfig symbols have now a formalized name
(CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)
- a new Kconfig.isa file was introduced with the full set of extensions
currently supported by the v2.2 spec
- a new Kconfig.core file was introduced to host all the RISCV cores
(currently only E31)
- ISA and extensions settings are moved to SoC configuration files
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This PR adds a soft off mode to the RT10xx Power Management API.
Additionally, it corrects the PM API function in rt10xx_power.c to
use the correct function prototype to be properly overridden.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
Make the intel_adsp west runner starting to work on all the
intel_adsp boards. Changes include:
1. Make the cavstool.py work as a service in remote host
ADSP board and rename it to cavstool_server.py.
2. Active the runner and adds a common board.cmake file to
specify the default signing key for cavs boards.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
The cavstool_client.py is a client use to communicate with
the firmware loading and running server which dealing with
the requests from the intel_adsp west runner. It supports:
1. Download firmware to remote ADSP host and running.
2. Send the ADSP log messages back to client.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
There was a confusion on MB_MEMx definitions. Both MB_MEM1/2
should be located in SRAM1. Fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The current sam0 adc driver not implement correctly the adc_reference
enum values. This try homonize adc input referece by tracking VDDANA
at ADC_REF_VDD_1. The ADC_REF_VDD_1_2 were fixed with correct INTVCCx
channel selection.
Fixes#45443
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The stm32f7 (like stm32H7) should be able to disable
the Dcache when using the DMA. This is to avoid any
pb of cache coherency on the DMA buffers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update the new API to use K_USER as the flags for both
CONFIG_USERSPACE and CONFIG_TEST_USERSPACE. Also, fix the linker
script to properly include the suites, tests, and rules.
Fixes#44108
Signed-off-by: Yuval Peress <peress@google.com>
This commit adds a call to the Colorama initialisation function during
the module execution so that ANSI color sequences are properly
converted to the relevant Win32 API calls on the Windows.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit introduces changes in three places in order to fix the
problem with timer-related tests on FE310-based boards:
* tests/kernel/sleep/kernel.common.timing
* tests/kernel/tickless/tickless_concept/kernel.tickless.concept
* tests/kernel/workq/work_queue/kernel.workqueue
The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC
value back to 32768 Hz to match FE310's datasheet description.
The second change is CLINT frequency reduction in Renode simulation
model to 16 MHz to correspond with the oscillator frequency given by the
FE310's datasheet and the HiFive1 board schematic. This fixes the first
two tests.
The last change is reducing the MIN_DELAY define to 100. This causes the
RISC-V machine timer driver to update the mtimecmp register more often,
which in turn addresses the `work_queue/kernel.workqueue` problem with
work items finishing prematurely, causing the above-mentioned test to
fail.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Up till now the usage of CONFIG_NOCACHE_MEMORY also explicitly disables
data cache on the STM32H7 SoC.
With this change the usage of CONFIG_NOCACHE_MEMORY has been decoupled
from data cache enabling as new Kconfig option - namely
CONFIG_DCACHE is now used to explicitly enable it.
After this change it would be possible to use data cache on STM32H7
with DMA buffers, fragile to cache coherency issues, defined with
'__nocache' attribute.
Such approach would improve the overall STM32H7 performance until the
moment when proper (i.e. in-DMA) buffer cache management is developed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Config pwm open-drain mode without enabling STORE_REG. This CL
collects all active PWM's base address and related index in an
array. Then, pinctrl driver configs its open-drain mode by
finding the corresponding 'channel' index.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Set SYS_CLOCK_TICKS_PER_SEC to 128 for non-tickless kernel.
Previously it was set to 32768 disregarding kernel mode and that
lead to too frequent interrupts in non-tickless mode (tick every
30 us). Change to smaller value.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
ARCH_HAS_USERSPACE and ARCH_HAS_STACK_PROTECTION are direct functions
of RISCV_PMP regardless of the SoC.
PMP_STACK_GUARD is a function of HW_STACK_PROTECTION (from
ARCH_HAS_STACK_PROTECTION) and not the other way around.
This allows for tests/kernel/fatal/exception to test protection against
various stack overflows based on the PMP stack guard functionality.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
PHY TX power configuration must be added into soc level.
It was previously hardcoded in hal_espressif, which was removed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.
Fixes: #45611
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Updated PSoC 6 implementation to use hal_infineon/mtb-pdl-cat1
This PR is reflected changes according to Task#1 for RFC#42883.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
On STM32WB and dual-core STM32H7 MCUs, the RNG peripheral is shared
between the cores and its access is protected by a hardware semaphore.
Locking was not performed in the current entropy driver, leading to a
race condition when multiple cores concurrently used the RNG. This
commit implements the necessary logic for locking the HSEM during entropy
generation on multi-core STM32 MCUs. It also reconfigures the RNG in case
the configuration was changed by the other core, as this can happen e.g
on STM32WB MCUs.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
Add initial pin control support for the A53 core of the imx8mm. Since
the UART console driver is not currently enabled for this platform,
there is no way to test the full pin control enablement. Therefore,
CONFIG_PINCTRL is still not selected for this platform, although the
required DTS definitions and pin control headers are present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
