Previously, the `uart_console_isr()` routine assumed that the
return value of several uart API functions would only ever
return the equivalent of a boolean value. In fact, an integer
is returned on occasion, and that integer can take on many
values.
Since unary operations would either go to "true" or "false"
and since any non-zero integer evaluates to "true", even a
return value of something like `-ENODEV` would evalueate
to true.
Explicitly compare against the integer-equivalent value of
the expected boolean output.
With this, in the case of errors, negative return values do
not evaluate to "true", and the infinite loop is avoied.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Currently, the driver imply understand that all instances
will use dma when CONFIG_SPI_MCUX_LPSPI_DMA is set. There
might be an instance doesn't need DMA, so instead of enforce
spi_transceive API to use DMA, add more flexible to enable
DMA only when required
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
When the alternate setting is configured as func3, in addition to
the setting of func3-gcr, some pins require external setting.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Implement the RTIO/Sensors V2/Async API for the AKM09918C. Add a decoder
API implementation as well.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
Update the decoder APIs to vertically decode the raw sensor data. This
means that instead of getting each channel on a frame by frame basis,
the API takes a channel specifier and returns as many frames of that
given channel as there's room.
The goal of this is to make the end decoded result the most useful and
usable for the Zephyr application. See #60944 for details.
Signed-off-by: Yuval Peress <peress@google.com>
With update to handle DSI transfer length in MIPI_DSI driver, the logic
can be removed from the RM67162 driver. The driver now will simply
continue writing data until the full buffer is sent.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for SMARTDMA transfers, and byte swapping of RGB565 data.
Additionally, the limits on TX data size have been impelemented in the
MIPI DSI driver, as opposed to the RM67162 display where they were
previously added.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce SMARTDMA dma driver. The SMARTDMA is a peripheral present on
some NXP SOCs, which implements a programmable DMA engine. The DMA
engine does not use channels, but rather provides a series of API
functions implemented by the firmware provided with MCUX SDK.
These API functions can be selected by the dma_config slot parameter. A
custom API is also provided to allow the user to install an alternate
firmware into the SMARTDMA.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Limit DSI data TX to the max payload size possible with this peripheral,
rather than relying on display drivers to respect this limitation.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix the assignment of initial CAN bus timing parameters for the CAN-FD data
phase.
Fixes: #62979
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add MDIO driver that works through GPIO pins. This driver is
useful when a microcontroller doesn't have MDIO bus or when multiple
separate MDIO buses are required. The driver provides access to
the MDIO bus through GPIO pins for any SoC that has GPIO pin control
available.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Switch from using DEVICE_DT_DEFINE()/DEVICE_DT_INST_DEFINE() to using
CAN_DEVICE_DT_DEFINE()/CAN_DEVICE_DT_INST_DEFINE() for remaining drivers.
This unifies CAN controller device driver initialization regardless of the
driver implementing CAN statistics support or not.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove CHANNEL_COUNT limit used to check the channel bitmask.
This value was not applicable on STM32L1 where channel can go up to 31.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove unwanted "pm_device_runtime_get" lock which makes i2c power
management working incorrectly.
Fixes: #62790
Signed-off-by: Petr Hlineny <development@hlineny.cz>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This fixes the following compile time warning;
drivers/mm/mm_drv_intel_adsp_mtl_tlb.c: In function 'sys_mm_drv_mm_init':
include/zephyr/sys/__assert.h:44:52: error: format '%p' expects argument
of type 'void *', but argument 2 has type
'long unsigned int' [-Werror=format=]
__ASSERT_PRINT("\t" fmt "\n", ##__VA_ARGS__)
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
The PIT maximum load value may not be always 32-bit. Allow the SoC to
define this value from devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Depending on the SoC design, the PIT channel interrupts can be
individual or OR'ed together to a single interrupt line.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This periodic timer (PIT) has a single load value register for each
channel, which is currently used for both alarm and top callback APIs.
If using both APIs together (which is a valid use-case) it will write
to the same register causing unexpected behavior of the timer.
The nature of the PIT is to trigger an event (like interrupts) at a
certain rate, and not to produce single-shot events. Hence keep only top
callback functionality.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This is a specific case for NVMe where given data buffer pointers must
be dword (4 bytes) aligned.
There is no virtual memory management between the user thread and NVMe
driver (which one could detect such wrong alignement on physical memory
and thus reallocate the memory properly, so it would be fully
transparent for the user thread), thus the need to push that check to
the user.
This has been going under the radar so far as Qemu does not seem to
follow NVMe specifications where PRP1 (in DPTR) must always be
dword-aligned. It really does not follow the rule: specifications
details that if bits 1:0 of PRP1 are set, the controller may generate
an error or treat the address as if these bits were unset. Seems like
a bug in Qemu, I did not check the code there however.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Former way was difficult to read, so let's have a better way which
easily follows the specifications.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will provide a detailed error status report.
As for most of the original code of the driver, this is a backport of
the work done by Jim Harris in FreeBSD.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert DEVICE_DEFINE to DEVICE_DT_INST_DEFINE, this allows the build
system to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Adjust some DT_INST macro as well while at it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Fix an incorrectly declared compatible and adjust some DT macros as
well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
On some STM32 families (such as F4), temperature and Vbat sensor share the
same ADC channel, which can lead to conflict when reading them, and wrong
measurement can follow.
To alleviate this problem, this commit moves the setting of the common
path internal channel to the sensor drivers themselves instead of doing
it in the ADC driver.
The teardown is still done in the ADC driver, systematically, instead of
channel by channel (which has the same result).
By moving this logic in the sensor drivers, the properties temp-channel,
vbat-channel and vref-channel becomes useless and are thus removed.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Introduce hwinfo driver for Texas Instruments SimpleLink CC13xx/CC26xx
SOC series, with support for retrieving device's ID and cause of reset.
By default, the pre-programmed, 8-bytes length IEEE MAC address is used
for device's ID, with option ('HWINFO_CC13XX_CC26XX_USE_BLE_MAC') for
use 6-bytes length BLE MAC instead. By default, read-only values stored
in FCFG (Factory Configuration) are used but additional Kconfig option
('HWINFO_CC13XX_CC26XX_ALWAYS_USE_FACTORY_DEFAULT') is also provided,
which allows to use values from writable CCFG (Customer Configuration)
area. In all cases, device ID value is provided in big-endian which
matches what TI's UniFlash tool returns.
For reset cause, 'SysCtrlResetSourceGet()' function from TI's driver
library is used and its value is mapped to Zephyr's implementation.
Importantly, only root cause of reset is available on CC13xx/CC26xx
platform as described in MCU Technical Reference Manual ('RESET_SRC'
field in 'RESETCTL' register):
"Shows the root cause of the last system reset. More than the
reported reset source can have been active during the last
system reset but only the root cause is reported."
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add CAN stats for MCAN drivers.
Update MCAN drivers to use CAN_DEVICE_DT_INST_DEFINE
which initialises and registers CAN stats if enabled.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
A file just named `init.c` is not that descriptive inside of a project
that has a lot of files of already. Rename to `ethos_u.c`.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The Ethos-U driver was using IRQ_DIRECT_CONNECT. This is not what the
driver needs as this will not detect a context switch when coming out
of the isr, and this is needed as the isr will release a semaphore.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add phandle prop to reference any regulator that must
be enabled in order for the LPADC to function as intended.
Change LPADC driver to use this property if present.
LPADC on LPC55S36 depends on VREF peripheral, enable for this platform.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
