drivers: adc: rework stm32 adc sequencer
Add sequencer support for all STM32 series. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier
Carles Cufí
parent
6d6d7b5607
commit
c201d21964
1 changed files with 136 additions and 93 deletions
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@ -68,18 +68,18 @@ LOG_MODULE_REGISTER(adc_stm32);
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num_sampling_time_common_channels,\
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0, value) 0)
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#define ANY_ADC_SEQUENCER_TYPE_IS(value) \
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(DT_INST_FOREACH_STATUS_OKAY_VARGS(IS_EQ_PROP_OR, \
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st_adc_sequencer,\
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0, value) 0)
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#define IS_EQ_PROP_OR(inst, prop, default_value, compare_value) \
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IS_EQ(DT_INST_PROP_OR(inst, prop, default_value), compare_value) ||
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/* reference voltage for the ADC */
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#define STM32_ADC_VREF_MV DT_INST_PROP(0, vref_mv)
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#if !defined(CONFIG_SOC_SERIES_STM32C0X) && \
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!defined(CONFIG_SOC_SERIES_STM32F0X) && \
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!defined(CONFIG_SOC_SERIES_STM32G0X) && \
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!defined(CONFIG_SOC_SERIES_STM32L0X) && \
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!defined(CONFIG_SOC_SERIES_STM32WBAX) && \
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!defined(CONFIG_SOC_SERIES_STM32WLX)
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#if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
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#define RANK(n) LL_ADC_REG_RANK_##n
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static const uint32_t table_rank[] = {
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RANK(1),
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@ -98,6 +98,22 @@ static const uint32_t table_rank[] = {
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RANK(14),
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RANK(15),
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RANK(16),
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#if defined(LL_ADC_REG_RANK_17)
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RANK(17),
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RANK(18),
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RANK(19),
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RANK(20),
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RANK(21),
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RANK(22),
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RANK(23),
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RANK(24),
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RANK(25),
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RANK(26),
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RANK(27),
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#if defined(LL_ADC_REG_RANK_28)
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RANK(28),
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#endif /* LL_ADC_REG_RANK_28 */
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#endif /* LL_ADC_REG_RANK_17 */
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};
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#define SEQ_LEN(n) LL_ADC_REG_SEQ_SCAN_ENABLE_##n##RANKS
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@ -119,8 +135,24 @@ static const uint32_t table_seq_len[] = {
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SEQ_LEN(14),
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SEQ_LEN(15),
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SEQ_LEN(16),
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#if defined(LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS)
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SEQ_LEN(17),
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SEQ_LEN(18),
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SEQ_LEN(19),
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SEQ_LEN(20),
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SEQ_LEN(21),
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SEQ_LEN(22),
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SEQ_LEN(23),
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SEQ_LEN(24),
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SEQ_LEN(25),
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SEQ_LEN(26),
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SEQ_LEN(27),
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#if defined(LL_ADC_REG_SEQ_SCAN_ENABLE_28RANKS)
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SEQ_LEN(28),
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#endif /* LL_ADC_REG_SEQ_SCAN_ENABLE_28RANKS */
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#endif /* LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS */
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};
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#endif
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#endif /* ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE) */
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/* External channels (maximum). */
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#define STM32_CHANNEL_COUNT 20
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@ -167,6 +199,7 @@ struct adc_stm32_cfg {
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const struct pinctrl_dev_config *pcfg;
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const uint16_t sampling_time_table[STM32_NB_SAMPLING_TIME];
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int8_t num_sampling_time_common_channels;
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int8_t sequencer_type;
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int8_t res_table_size;
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const uint32_t res_table[];
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};
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@ -724,6 +757,70 @@ static int set_resolution(const struct device *dev,
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return 0;
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}
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static int set_sequencer(const struct device *dev)
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{
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const struct adc_stm32_cfg *config = dev->config;
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struct adc_stm32_data *data = dev->data;
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ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
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uint8_t channel_id;
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uint8_t channel_index = 0;
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uint32_t channels_mask = 0;
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/* Iterate over selected channels in bitmask keeping track of:
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* - channel_index: ranging from 0 -> ( data->channel_count - 1 )
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* - channel_id: ordinal position of channel in data->channels bitmask
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*/
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for (uint32_t channels = data->channels; channels;
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channels &= ~BIT(channel_id), channel_index++) {
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channel_id = find_lsb_set(channels) - 1;
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uint32_t channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL(channel_id);
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channels_mask |= channel;
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#if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
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if (config->sequencer_type == FULLY_CONFIGURABLE) {
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#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32U5X)
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/*
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* Each channel in the sequence must be previously enabled in PCSEL.
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* This register controls the analog switch integrated in the IO level.
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*/
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LL_ADC_SetChannelPreselection(adc, channel);
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#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32U5X */
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LL_ADC_REG_SetSequencerRanks(adc, table_rank[channel_index], channel);
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LL_ADC_REG_SetSequencerLength(adc, table_seq_len[channel_index]);
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}
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#endif /* ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE) */
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}
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#if ANY_ADC_SEQUENCER_TYPE_IS(NOT_FULLY_CONFIGURABLE)
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if (config->sequencer_type == NOT_FULLY_CONFIGURABLE) {
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LL_ADC_REG_SetSequencerChannels(adc, channels_mask);
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#if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
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!defined(CONFIG_SOC_SERIES_STM32L0X) && \
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!defined(CONFIG_SOC_SERIES_STM32U5X) && \
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!defined(CONFIG_SOC_SERIES_STM32WBAX)
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/*
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* After modifying sequencer it is mandatory to wait for the
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* assertion of CCRDY flag
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*/
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while (LL_ADC_IsActiveFlag_CCRDY(adc) == 0) {
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}
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LL_ADC_ClearFlag_CCRDY(adc);
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#endif /* !CONFIG_SOC_SERIES_STM32F0X && !L0X && !U5X && !WBAX */
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}
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#endif /* ANY_ADC_SEQUENCER_TYPE_IS(NOT_FULLY_CONFIGURABLE) */
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) || \
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DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
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LL_ADC_SetSequencersScanMode(adc, LL_ADC_SEQ_SCAN_ENABLE);
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#endif /* st_stm32f1_adc || st_stm32f4_adc */
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return 0;
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}
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static int start_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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@ -747,22 +844,20 @@ static int start_read(const struct device *dev,
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return -EINVAL;
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}
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#if !defined(CONFIG_SOC_SERIES_STM32C0X) && \
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!defined(CONFIG_SOC_SERIES_STM32F0X) && \
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!defined(CONFIG_SOC_SERIES_STM32G0X) && \
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!defined(CONFIG_SOC_SERIES_STM32L0X) && \
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!defined(CONFIG_SOC_SERIES_STM32WBAX) && \
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!defined(CONFIG_SOC_SERIES_STM32WLX)
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#if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
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if (data->channel_count > ARRAY_SIZE(table_seq_len)) {
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LOG_ERR("Too many channels for sequencer. Max: %d", ARRAY_SIZE(table_seq_len));
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return -EINVAL;
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}
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#else
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#endif /* ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE) */
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && !defined(CONFIG_ADC_STM32_DMA)
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/* Multiple samplings is only supported with DMA for F1 */
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if (data->channel_count > 1) {
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LOG_ERR("This device only supports single channel sampling");
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LOG_ERR("Without DMA, this device only supports single channel sampling");
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return -EINVAL;
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}
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#endif
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && !CONFIG_ADC_STM32_DMA */
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/* Check and set the resolution */
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err = set_resolution(dev, sequence);
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@ -770,77 +865,10 @@ static int start_read(const struct device *dev,
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return err;
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}
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uint8_t channel_id;
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uint8_t channel_index = 0;
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/* Iterate over selected channels in bitmask keeping track of:
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* - channel_index: ranging from 0 -> ( data->channel_count - 1 )
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* - channel_id: ordinal position of channel in data->channels bitmask
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*/
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for (uint32_t channels = data->channels; channels;
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channels &= ~BIT(channel_id), channel_index++) {
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channel_id = find_lsb_set(channels) - 1;
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uint32_t channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL(channel_id);
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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/*
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* Each channel in the sequence must be previously enabled in PCSEL.
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* This register controls the analog switch integrated in the IO level.
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*/
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LL_ADC_SetChannelPreSelection(adc, channel);
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#elif defined(CONFIG_SOC_SERIES_STM32U5X)
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/*
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* Each channel in the sequence must be previously enabled in PCSEL.
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* This register controls the analog switch integrated in the IO level.
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* Only for ADC1 instance (ADC4 has no Channel preselection capability).
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*/
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if (adc == ADC1) {
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LL_ADC_SetChannelPreselection(adc, channel);
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}
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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LL_ADC_REG_SetSequencerChannels(adc, channel);
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#elif defined(CONFIG_SOC_SERIES_STM32WLX)
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/* Init the the ADC group for REGULAR conversion*/
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LL_ADC_REG_SetSequencerConfigurable(adc, LL_ADC_REG_SEQ_CONFIGURABLE);
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LL_ADC_REG_SetTriggerSource(adc, LL_ADC_REG_TRIG_SOFTWARE);
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LL_ADC_REG_SetSequencerLength(adc, LL_ADC_REG_SEQ_SCAN_DISABLE);
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LL_ADC_REG_SetOverrun(adc, LL_ADC_REG_OVR_DATA_OVERWRITTEN);
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LL_ADC_REG_SetSequencerRanks(adc, LL_ADC_REG_RANK_1, channel);
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LL_ADC_REG_SetSequencerChannels(adc, channel);
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/* Wait for config complete config is ready */
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while (LL_ADC_IsActiveFlag_CCRDY(adc) == 0) {
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}
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LL_ADC_ClearFlag_CCRDY(adc);
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#elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32G0X)
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/* C0 and G0 in "not fully configurable" sequencer mode */
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LL_ADC_REG_SetSequencerChannels(adc, channel);
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LL_ADC_REG_SetSequencerConfigurable(adc, LL_ADC_REG_SEQ_FIXED);
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while (LL_ADC_IsActiveFlag_CCRDY(adc) == 0) {
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}
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LL_ADC_ClearFlag_CCRDY(adc);
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#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
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LL_ADC_REG_StopConversion(adc);
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while (LL_ADC_REG_IsStopConversionOngoing(adc) != 0) {
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}
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LL_ADC_REG_SetSequencerChannels(adc, channel);
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LL_ADC_REG_SetSequencerConfigurable(adc, LL_ADC_REG_SEQ_FIXED);
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#elif defined(CONFIG_SOC_SERIES_STM32U5X)
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if (adc != ADC4) {
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LL_ADC_REG_SetSequencerRanks(adc, table_rank[channel_index], channel);
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LL_ADC_REG_SetSequencerLength(adc, table_seq_len[channel_index]);
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} else {
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LL_ADC_REG_SetSequencerConfigurable(adc, LL_ADC_REG_SEQ_FIXED);
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LL_ADC_REG_SetSequencerLength(adc,
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BIT(__LL_ADC_CHANNEL_TO_DECIMAL_NB(channel)));
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}
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#else
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LL_ADC_REG_SetSequencerRanks(adc, table_rank[channel_index], channel);
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LL_ADC_REG_SetSequencerLength(adc, table_seq_len[channel_index]);
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#endif
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/* Configure the sequencer */
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err = set_sequencer(dev);
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if (err < 0) {
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return err;
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}
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err = check_buffer(sequence, data->channel_count);
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@ -886,6 +914,8 @@ static int start_read(const struct device *dev,
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#if !defined(CONFIG_ADC_STM32_DMA)
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
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/* Trigger an ISR after each sampling (not just end of sequence) */
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LL_ADC_REG_SetFlagEndOfConversion(adc, LL_ADC_REG_FLAG_EOC_UNITARY_CONV);
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LL_ADC_EnableIT_EOCS(adc);
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
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LL_ADC_EnableIT_EOS(adc);
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@ -939,12 +969,19 @@ static void adc_stm32_isr(const struct device *dev)
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(const struct adc_stm32_cfg *)dev->config;
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ADC_TypeDef *adc = config->base;
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*data->buffer++ = LL_ADC_REG_ReadConversionData32(adc);
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/* ISR is triggered after each conversion, and at the end-of-sequence. */
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if (++data->samples_count == data->channel_count) {
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data->samples_count = 0;
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adc_context_on_sampling_done(&data->ctx, dev);
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
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if (LL_ADC_IsActiveFlag_EOS(adc) == 1) {
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
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if (LL_ADC_IsActiveFlag_EOCS(adc) == 1) {
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#else
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if (LL_ADC_IsActiveFlag_EOC(adc) == 1) {
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#endif
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*data->buffer++ = LL_ADC_REG_ReadConversionData32(adc);
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/* ISR is triggered after each conversion, and at the end-of-sequence. */
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if (++data->samples_count == data->channel_count) {
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data->samples_count = 0;
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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LOG_DBG("%s ISR triggered.", dev->name);
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@ -963,6 +1000,11 @@ static void adc_context_on_complete(struct adc_context *ctx, int status)
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adc_stm32_disable(adc);
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LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(adc),
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LL_ADC_PATH_INTERNAL_NONE);
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#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32U5X)
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/* Reset channel preselection register */
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LL_ADC_SetChannelPreselection(adc, 0);
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#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32U5X */
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}
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static int adc_stm32_read(const struct device *dev,
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@ -1450,6 +1492,7 @@ static const struct adc_stm32_cfg adc_stm32_cfg_##index = { \
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.pclk_len = DT_INST_NUM_CLOCKS(index), \
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.clk_prescaler = ADC_STM32_DT_PRESC(index), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
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.sequencer_type = DT_INST_PROP(index, st_adc_sequencer), \
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.sampling_time_table = DT_INST_PROP(index, sampling_times), \
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.num_sampling_time_common_channels = \
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DT_INST_PROP_OR(index, num_sampling_time_common_channels, 0),\
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