Commit graph

117429 commits

Author SHA1 Message Date
Alain Volmat
d33f579684 soc: st: stm32: set default video buffer align to 16 for DCMIPP
Set the default video buffer alignment constraint to 16 when DCMIPP
is being used.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-19 13:57:51 +02:00
Alain Volmat
7640180e7c soc: st: stm32: set default SMH attribute for LTDC/video buffers
The SMH attribute when using the XSPI PSRAM is set to EXTERNAL (2)
within the driver hence set default for both LTDC and video
buffer SMH attribute to 2 if all conditions are validated.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-19 13:57:51 +02:00
Alain Volmat
b1e55bd342 display: stm32: ltdc: add SMH buffer alignment config option
Add the CONFIG_STM32_LTDC_FB_SMH_ALIGN option in order to
indicate the alignment required for the buffer allocated via
SMH.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-19 13:57:51 +02:00
Alain Volmat
b7f73710b2 memc: stm32_xspi_psram: init shared_multi_heap area
Initialize the whole psram as a shared_multi_heap_area
if SHARED_MULTI_HEAP is enabled.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-19 13:57:51 +02:00
Khaoula Bidani
2a623605ab tests: drivers: dac: dac_api: update dac_api test
-add nucleo_u385rg_q to dac_api test

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-19 13:57:36 +02:00
Khaoula Bidani
69c2ce0d61 boards: st: add dac node in dts file and update docs
- enable dac in nucleo_u385rg_q
- add dac as new supported interface in docs
- update yaml files

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-19 13:57:36 +02:00
Khaoula Bidani
20d4ab149e dts: arm: st: u3: add dac node in dtsi file
all stm32u3 boards have only one and same
dac peripheral.

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-19 13:57:36 +02:00
Jamie McCrae
e5f32b812b samples: sysbuild: with_mcuboot: Fix Kconfig setting
Removes a superfluous Kconfig for setting the MCUboot operating
mode as sysbuild does this automatically, adds a comment about why
it is omitted, and then sets it in the correct place

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-19 13:57:15 +02:00
Benjamin Cabé
043bb58488 doc: ci: Zephyr now requires Python 3.12 or higher
Update getting started guide, release notes, CI actions and
Python version compliance check to use Python 3.12 as
minimum supported version.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-19 13:56:59 +02:00
Tahsin Mutlugun
b9bfff29f4 doc: arch: semihost: Add Xtensa support
Add information about Xtensa semihosting.

Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
2025-06-19 09:36:42 +02:00
Tahsin Mutlugun
784b3d6ea0 arch: xtensa: Add semihosting support
Add semihosting support for Xtensa architecture.

Existing semihosting instructions are based on ARM, so they are
converted to Xtensa codes before the semihosting call is invoked.

Return codes of read, write and seek calls had to be converted to match
semihosting API definitions.

Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
2025-06-19 09:36:42 +02:00
Tahsin Mutlugun
38d0300035 arch: common: semihost: Move semihost structs into a separate header
Move semihost_x_args structs to include/semihost_types.h so that
semihost implementations can access their elements if needed.

Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
2025-06-19 09:36:42 +02:00
YongWoo Kang
d5098a2a30 boards: nucleo_f411r: fix ram size to 128KB
Nucleo F411RE(STM32F411RET6) is provides 128 Kbytes of SRAM.

Link: https://www.st.com/en/microcontrollers-microprocessors/stm32f411re.html [1]
Link: https://docs.zephyrproject.org/latest/boards/st/nucleo_f411re/doc/index.html [2]

Signed-off-by: YongWoo Kang <kyw0708@kumoh.ac.kr>
2025-06-19 09:36:34 +02:00
Marek Matej
648bfe090c soc: espressif: Support large buffers in custom PSRAM sections
Several subsystems have configuration options that allow large buffers
to be placed in specialized memory sections. When PSRAM is enabled, the
MBEDTLS heap and LVGL heap and buffer can be relocated to custom sections
within the PSRAM segment.

Enabling `CONFIG_ESP_SPIRAM` together with any of the following options:
* `CONFIG_MBEDTLS_HEAP_CUSTOM_SECTION`
* `CONFIG_LV_Z_MEMORY_POOL_CUSTOM_SECTION`
* `CONFIG_LV_Z_VDB_CUSTOM_SECTION`

will place the corresponding buffers into the `.mbedtls_heap`,
`.lvgl_heap`, and `.lvgl_buf` sections, respectively.
If none of these custom section options are enabled, the buffers will
fall back to the `.ext_ram.bss` section.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-06-19 09:36:27 +02:00
Benjamin Cabé
bb983d09bf ci: workflows: remove unsupported Python version from test matrices
Python 3.10 and 3.11 are no longer supported so drop them from the
GitHub Actions test matrices.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-19 09:36:17 +02:00
Benjamin Cabé
eff39fb70a tests: fs: fat_fs_api: add native_sim to platform_allow
Native sim was inadvertently forgotten from the platform_allow list with
commit 257e56c.
It should be in there as it is an integration platform.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-19 08:05:14 +02:00
Peter Mitsis
2f2eaf7b6f arch: xtensa: Update arch_user_string_nlen()
When calling device_get_binding(NULL) from userspace, this eventually
funnels down to a call to arch_user_string_nlen() where it tried to
verify that the kernel has access to this address (0x0).  But since
this originates from userspace, we really want to know if this is
accessible from userspace, so using arch_buffer_validate() instead
of xtensa_mem_kernel_has_access() is preferable.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-06-19 00:03:00 +02:00
Peter Mitsis
dde9462666 arch: tweak xtensa_mem_kernel_has_access() API
Adds 'const' to address pointer as its memory contents
do not change.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-06-19 00:03:00 +02:00
Declan Snyder
84d2f7f4de spi_nxp_lpspi: Fix extra byte sent on v1 lpspi
This stupid errata will not leave me alone, here is another bandaid to
deal with an issue where an extra byte was being sent on version 1
LPSPIs due to the algorithm of filling NOPs when only RX is left was not
expecting the situation where the LPSPI actually consumed everything
from the fifo but is not sending it due to this ridiculous stalling errata.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Declan Snyder
f6a9a1f3bc spi_nxp_lpspi: Fix unit of buf_len in fill_tx_fifo
The buf_len parameter of lpspi_fill_tx_fifo is supposed to be bytes, so
we do not need to convert it. This could cause an issue if the end of
the buffer is less bytes than the word size.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Declan Snyder
e9d964f628 spi_nxp_lpspi: Fix fifo fill logic
Fixing some issues with the TX fifo fill logic in two places:

First in the normal fill function, it didn't take into account a
situation where the TX fifo is already partially filled. This currently
doesn't cause a problem because the driver is written in a way that the
watermark is always 0 for TDF, but in case the watermark were anything
else it would cause a problem.

Second, when filling the TX fifo with NOPS in order to clock the rest of
the RX in from the bus, the calculation regarding the current TX fifo
length was just wrong and was leading to a bug in some cases where there
was a subtraction underflow and billions of NOPs were being filled.
Also, there could be a problem where a few extra NOPs are put in the TX
fifo if we don't count what we already have in the TX fifo, so fixing
that as well.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Declan Snyder
7aa0778901 spi_nxp_lpspi: Simplify tx ctx update
There is no need to update the tx context in interrupt instead of
directly after the fill, this just makes the code more complex. Also,
the spi context header already handled iterating over buffers so we can
remove that code too.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Declan Snyder
877fa975cc spi_nxp_lpspi: Remove MCUX branding
Since the LPSPI drivers no long use MCUX at all, remove the MCUX
branding, to avoid confusion. In the future if an implementation uses
the MCUX SDK driver, it should specifically be called by MCUX in the
name.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Declan Snyder
2aad9ebb78 spi_nxp_lpspi: Remove call to MasterInit
For optimization purpose, remove calls to SDK. Since we know exactly
what we want, this results in smaller code size.

Also, this code calculates the SCK parameters more efficiently than the
SDK driver did it by using a binary (instead of linear) search.

Lastly, remove call to LPSPI_Reset in the init call and replace with
native driver code, and remove inclusion of SDK header.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Declan Snyder
c0e3ec7f08 spi_nxp_lpspi: Add maximum wait time of fifo empty
Instead of waiting forever and potentially allowing infinite loop on
ISR, wait some arbitrary amount of cycles to error out if it isn't
happening. Still make this configurable for debugging purposes.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Declan Snyder
691e7598ff spi_nxp_lpspi: Add version ID to data struct
Since I expect that the drivers will need to read this version ID maybe
multiple times, instead of repeatedly doing so over the peripheral bus,
it is probably worth it to store a byte in RAM representing this
version. The behavior of the LPSPI is fairly significantly different
between versions. Not enough to warrant separate drivers but enough to
need a few workarounds or different code branches depending on this.

Also, the interrupt based driver is currently using a wrong macro to
read this, and that is a bug.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Declan Snyder
aeedf86da6 spi_nxp_lpspi: Clarify configuration function
Clarify at the top of the common lpspi file what is the purpose of the
file to be clear to future developers that this file is not supposed to
make any assumption about a particular implementation of the zephyr API
using the LPSPI, because I imagine it could be very likely that more
lpspi implementation will be done in the future to make different
tradeoffs than the current two. Also the current two are different
enough that we should avoid making assumptions even if they currently
hold for both because they might not always, as things change.

We should disable interrupt events while configuring the LPSPI
regardless of implementation. The specific implementation should enable
the interrupts it needs on its own transceive implementation.

Also clarify and simplify some code in the configure function. Namely,
we no longer need to check if we are already configured to write to
registers because a recent commit made it so that we clock the
peripheral from the zephyr driver init instead of upon the MasterInit
call on the SDK. There is also a redundant CR write which I have removed.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Declan Snyder
2aa9ec43dc spi_nxp_lpspi: Remove dev pointer from data struct
The dev pointer in the data struct is not being used, so remove it.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:51:19 -04:00
Mahesh Mahadevan
db6ca32346 boards: rw612: Add code to configure the pins in PM Mode 3
These settings are used to put the pins in power saving mode
when we enter SUSPEND power mode.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2025-06-18 17:50:48 -04:00
Mahesh Mahadevan
bfd5fab28a drivers: pinctrl: Do not confgure sleep pins in NXP MCI IOMUX driver
The sleep-output property is no longer used. This results in the sleep
bit to be always cleared. Delete this code so we can retain any sleep
mode configuration done.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2025-06-18 17:50:48 -04:00
Pieter De Gendt
9ad5e8dc57 boards: shields: Add OpenThread RCP over Arduino header
Create a virtual shield to connect an OpenThread RCP radio device with a
host using the UART or SPI bus.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-06-18 17:50:31 -04:00
Pieter De Gendt
a540ee6143 drivers: hdlc_rcp_if: Add HDLC SPI adapter driver
Implement the HDLC over SPI adapter driver to support the Openthread RCP
with SPI communication.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-06-18 17:50:31 -04:00
Pieter De Gendt
b24085ddda drivers: hdlc_rcp_if: Select EVENTS
The HDLC platform implementation uses the k_event API.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-06-18 17:50:31 -04:00
Van Petrosyan
04057e15ec sensor: lps22hh: clang-format cleanup
Style-only reformatting, no functional change.

Signed-off-by: Van Petrosyan <van.petrosyan@sensirion.com>
2025-06-18 17:50:22 -04:00
Van Petrosyan
1aa07db0ae sensor: lps22hh: add device power management support
Registers driver with pm_device_driver_init(); implements TURN_ON,
SUSPEND and RESUME.  Sets ODR = 0 on suspend per datasheet

Signed-off-by: Van Petrosyan <van.petrosyan@sensirion.com>
2025-06-18 17:50:22 -04:00
Tim Pambor
9ab0c1b183 sys: timeutil: Fix warning in timespec_is_valid
Cast NSEC_PER_SEC to long to resolve a compiler warning about comparison
between signed and unsigned integer expression.

Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
2025-06-18 17:49:56 -04:00
Declan Snyder
93e9016775 boards: nxp: Change default mac to unique for some
Change the default of the mac address for a few example boards
to use the "unique" option based on the chip unique ID,
instead of random. The RW was chosen because it has HWINFO implemented
currently. RT1050 was chosen as one of the RT boards.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:49:41 -04:00
Declan Snyder
3d8196f41b drivers: nxp_enet: Use hwinfo API for unique mac
Use the HWINFO API for getting the unique mac address, and use the
pre-existing hardcoded macros as fallbacks if hwinfo is not implemented
properly.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-06-18 17:49:41 -04:00
Jamie McCrae
220d69893c west.yml: MCUboot synchronization from upstream
Update Zephyr fork of MCUboot to revision:
  11982df962e2314f4e0c73b7ebc17172026c9266

Brings following Zephyr relevant fixes:

  - 11982df9 boot: Switch to picolibc
  - ef7d68bf boot: zephyr: boards: delete mcxn947 configuration.
  - 47dc5086 boot: zephyr: update NXP MPU define to new name
  - 35536633 boot: bootutil: bootutil_misc: Fix max image size for
    single images
  - e8b22363 bootutil: Fix crash when bootutil_sha_init() is called
    in loop
  - 0eaf6668 boot: bootutil: Only update the security counter for
    confirmed images
  - 792d411d bootutil: encryption: Fix typo in PSA code
  - 2e605191 boot: bootutil: swap-offset: Fix image size check
    during validation
  - 61d280b9 boot: bootutil: Fix max image size computation for
    swap-move/swap-offset
  - 17b56a0a imgtool: fix verify tlv offset before main scan
  - 264f6ee9 boot/zephyr/main: fix placement of pointer to arm
    vector
  - c412cdfb bootutil: Improve HKDF code
  - 454cae8b bootutil: Remove BOOTUTIL_CRYPTO_AES_CTR_KEY_SIZE
  - 2367a607 bootutil: Improve defines in PSA encryption source
  - 3f458fea Bootutil: always initialise the size returned by
    boot_util_image_size()
  - 671513cb zephyr: nRF54l15_cpuapp configuration with LTO enabled

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-18 17:49:20 -04:00
John Shelton
3b2103f5f7 sensor: dht: Fix multi-instance type handling
The DHT driver incorrectly assumes all sensor instances are the same
type as the first instance (dht@0). The data parsing logic uses a
hardcoded check of the devicetree property for instance 0, which
causes incorrect readings when different sensor models (e.g., DHT11
and DHT22) are used together.

This change stores the model type in each per-instance config struct
during initialization. The data parsing logic is updated to use this
per-instance flag, ensuring each sensor is handled correctly
according to its specific model.

Signed-off-by: John Shelton <moosery@gmail.com>
2025-06-18 17:48:58 -04:00
Jamie McCrae
4af0a02b4c doc: services: device_mgmt: smp_groups: Add boot_mode details
Adds details on a new optional parameter for the OS mgmt reset
command which can specify the boot mode

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-18 17:48:44 -04:00
Jamie McCrae
0adcf2e66d mgmt: mcumgr: grp: os_mgmt: Add optional boot mode for reset
Adds an optional boot mode field which can be used to boot into a
specific image or mode using MCUmgr's OS mgmt reset command

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-18 17:48:44 -04:00
Andrej Butok
257e56c6d5 tests: fs: fat_fs_api: Add NXP platforms for filesystem.fat.ram.api
- Adds NXP platforms for the filesystem.fat.ram.api test case.
- Renames prj_native_ram.conf to prj_ram.conf,
  as it can be used by all platforms.

Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
2025-06-18 17:48:15 -04:00
Anas Nashif
72a8393aac kernel: kswap: removes unused arch_swap function declaration
Eliminates the external declaration of the `arch_swap` function.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-06-18 17:48:03 -04:00
Anas Nashif
41922b35e4 drivers: uart: make ISR function static to match existing declaration
Declaration of the same function should match and be static.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-06-18 17:48:03 -04:00
Anas Nashif
ccc8947d16 arm_mpu_v7m: add missing break statement in default case of writable check
add missing break statement in default case of writable check to satisfy
sca.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-06-18 17:48:03 -04:00
Anas Nashif
d20a52c4aa ztest: add missing break statement in ztest_test_pass function
Adds missing break in switch statement.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-06-18 17:48:03 -04:00
Anas Nashif
d4a2b7dc57 lib: os: cbprintf_complete: add missing break statement
Add missing break in switch statement.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-06-18 17:48:03 -04:00
Anas Nashif
9dc30f8dec x86: mmu: add missing break statement in flags_to_entry function
Add missing break in switch statement.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-06-18 17:48:03 -04:00
Anas Nashif
0ca2a9ed4c arch: x86: multiboot: add a break in default switch case
Add missing break in switch statement.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-06-18 17:48:03 -04:00