What is changed?
Use CMSIS SystemCoreClock via a dedicated flag instead of using
soc flags.
Why do we need this change?
This change is part of cleaning soc specific code out of arch folder.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The FRDM_MCXW71 Platform has a reserved IRQ as its
last IRQ, this test was using this IRQ to
test an interrupt and would not fire. This change
ensures the test does not use the reserved IRQ.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
When option ARM_MPU is disabled exclude soc\nxp\imxrt\mpu_regions.c.
It is needed to remove constraints of SRAM and FLASH size.
Fixes#70920
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
As for the IMX SOCs all the lines removed in this commit were
actually commented out so there's basically no change in code
behavior expected here.
The only affected SOCs family is therefore the Kinetis one.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
RT11xx SOC init should check to see if the zephyr flash node is
set to a device on the FLEXSPI bus to determine if the part is running
in XIP mode. This check was incorrect, so the FLEXSPI was being
reclocked in XIP mode to 24 MHz. Fix this check so the FlexSPI is not
downclocked.
Fixes#75702
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Do not select HAS_SEGGER_RTT unless the segger module is present. This
avoids a Kconfig error when SEGGER's debug module is not present in the
west manifest
Fixes#80529
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
There is a typo in the part number list for LPC55S69. The
LPC55S69JET98 should be LPC55S69JEV98.
Fixes#80541
Signed-off-by: David Leach <david.leach@nxp.com>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
HAS_SEGGER_RTT Kconfix symbol is missing in NXP MCXC series Kconfig.
Add the symbol to fix and enable Segger RTT samples.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Bandgap voltage is used for on die temperature measurement. Bandgap
buffer has to be enabled explicitly to get correct tempearature.
Enable the buffer if TEMP_KINETIS is selected.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
- add ITCM definitions (for LinkServer) in board.cmake
- update of soc.c to support RAM images (stack pointer)
- doc update
Change applies to both versions of the MIMXRT1170 EVK
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
support the configurations which apply for LVDS pads
+ termination resistor
+ current reference control
+ rx current boost
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
IMXRT1062 bootrom reads boothdr initial vector table
from 0x60001000. In the CMAKE scatter linker scripts we put multiple
sections at offset 0x1000 in the rom. In linkers other than LD, we are
not guaranteed a particular order when placing these.
If we specify FIRST we can count on the .ivt coming first. The other
positions aren't as crucial.
From IMXRT1060RM.pdf 9.7.1
> The location of the IVT is the only fixed requirement by the ROM.
> The remainder or the image memory map is flexible and
> is determined by the contents of the IVT.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
This config will be used to indicate if a platform
has the support for monolithic BT feature.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
- Disables on reset NMI and EzPort.
- Fixes frdm-k64 SW3 user button on reset issue.
So it can be assigned to the mcuboot-button0 alias.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
SOC_FLASH_MCUX has additional dependencies for LPC55xxx CPUs, due to the
fact that the flash should be disabled when executing in nonsecure mode.
Since the merge of HWMv2, this dependency has been set incorrectly at
the SOC level, resulting in the IAP flash driver being enabled when
targeting CPU1, which is incorrect. Fix the Kconfig dependency to
resolve this issue.
Fixes#79576
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some imx8 socs have cpu cluster entries for cores that
are not currently supported. Remove them.
Fixes#79027.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add resource_table section in linker script for i.MX8QXP and
i.MX8QM, for inter-process communication.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add DT node and clocking of TPM peripherals, which are used for PWM.
Also change the soc clock enable code to not use preprocessor
conditionals.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Base enablement of MCXW merged while z_arm_platform_init was being
deprecated, resulting situation is now that no platform init is
happening, fix by converting to use soc_reset_hook.
Also fix a comment that said the core was being set to 40 MHz, when it
is actually being set up to 96 MHz.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Update RT5xx and RT6xx clock init to add the code
to set the I3C dividers. This code has been moved
from the I3C driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Reverts bus clock settings. Follows MCUXpresso SDK clock settings, and
sets to output of SysPLL2 PFD3 at 198 MHz.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Timer/PWM Module (TPM) initial clock source is not selected.
Add initial clock source selection based on Devicetree configuration.
Rename clock sources definitions from LPUART specific to general names
usable by several modules on the SoC.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
