soc: nxp: imxrt118x: enable and configure M33 MPU
Enabled and configured M33 MPU. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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3 changed files with 37 additions and 0 deletions
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@ -7,6 +7,7 @@
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zephyr_sources(soc.c)
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if(CONFIG_SOC_MIMXRT1189_CM33)
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zephyr_sources(m33/mpu_regions.c)
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zephyr_linker_sources(DTCM_SECTION m33/dtcm.ld)
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endif()
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@ -12,6 +12,8 @@ config SOC_SERIES_IMXRT118X
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select CPU_HAS_ARM_SAU if SOC_MIMXRT1189_CM33
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select HAS_MCUX
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select CPU_HAS_ARM_MPU
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS if SOC_MIMXRT1189_CM33
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select ARM_MPU if SOC_MIMXRT1189_CM33
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select INIT_ARM_PLL
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select ARM_TRUSTZONE_M if SOC_MIMXRT1189_CM33
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select CPU_HAS_ICACHE if SOC_MIMXRT1189_CM7
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34
soc/nxp/imxrt/imxrt118x/m33/mpu_regions.c
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34
soc/nxp/imxrt/imxrt118x/m33/mpu_regions.c
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@ -0,0 +1,34 @@
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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
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#define REGION_HYPERRAM_BASE_ADDRESS 0x04000000
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#define REGION_HYPERRAM_SIZE 0x04000000
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#define REGION_DTCM_BASE_ADDRESS 0x20000000
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#define REGION_DTCM_SIZE 0x00020000
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#define REGION_FLEXSPI_BASE_ADDRESS 0x28000000
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#define REGION_FLEXSPI_SIZE 0x08000000
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#define REGION_PERIPHERAL_BASE_ADDRESS 0x40000000
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#define REGION_PERIPHERAL_SIZE 0x40000000
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static const struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("HYPERRAM", REGION_HYPERRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_HYPERRAM_BASE_ADDRESS, REGION_HYPERRAM_SIZE)),
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MPU_REGION_ENTRY("FLEXSPI", REGION_FLEXSPI_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_FLEXSPI_BASE_ADDRESS, REGION_FLEXSPI_SIZE)),
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MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS,
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REGION_RAM_NOCACHE_ATTR(REGION_DTCM_BASE_ADDRESS, REGION_DTCM_SIZE)),
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MPU_REGION_ENTRY(
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"PERIPHERAL", REGION_PERIPHERAL_BASE_ADDRESS,
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REGION_DEVICE_ATTR(REGION_PERIPHERAL_BASE_ADDRESS, REGION_PERIPHERAL_SIZE)),
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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