Commit graph

5563 commits

Author SHA1 Message Date
Jelle De Vleeschouwer
685c0e0662 boards: nucleo_wl55jc: assert SRST before any target connection
Failed to flash blinky example to stock nucleo_wl55jc due to default
application entering low power mode using WFI. To connect to a sleeping
stm32wl55 a system reset is required.

Signed-off-by: Jelle De Vleeschouwer <jelledevleeschouwer@gmail.com>
2021-11-23 10:33:37 -05:00
Peter Johanson
d99de305ce dts: bindings: Add generic Xiao interconnect
* With existence of Adafruit Qt Py boards, and upcoming wireless
  Xiao from Seeeduino, define nexus node and peripheral node
  labels for use with shields that accept any Xiao format board.
* Adds `&xiao_d`, `&xiao_spi`, `&xiao_i2c` and `&xiao_serial` generic
  node labels.
* Add new 'seeed-xioa-header.yaml` to document new nexus node.

Signed-off-by: Peter Johanson <peter@peterjohanson.com>
2021-11-22 22:25:20 -05:00
Fabio Baltieri
106f82013b boards: lora_e5_dev_board: set defaults for blackmagicprobe
This sets the commonly used serial port alias for blackmagicprobe, as
well as the flag to reset on connect, so that flashing works in low
power.

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
2021-11-22 22:20:02 -05:00
Fabio Baltieri
a85b5f5fe2 boards: lora_e5_dev_board: add power states config
Add the power state configs so that the board can be used with suspend
to idle out of the box. This is the same config as the one in
nucleo_wl55jc.

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
2021-11-22 22:20:02 -05:00
Joakim Andersson
3db41349f5 cmake: Add variable for the TFM build directory
The TFM build directory path is hardcoded in many places.
In order to support out-of-tree secure partitions the output path
has to be known in potentially out-of-tree build scripts.
This could potentially break out-of-tree build scripts if the
location of the build directory was changed.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2021-11-22 22:19:41 -05:00
Gerard Marull-Paretas
d702e74854 boards: gd32f403z_eval: use pinctrl
Enable usage of pinctrl.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
37c855f3c8 boards: gd32f450i_eval: use pinctrl
Enable usage of the pinctrl driver.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Yasushi SHOJI
4b6db52798 boards/arm/*/doc: Fix numbered list syntax in .rst
For reStructuredText, continuing text in a numbered list must be aligned
to the first line.

These lines are searched by the following regex:

    ag '#\. .*\n[^ #\n]' **/*.rst

Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
2021-11-22 08:30:53 -05:00
Ruibin Chang
b0cbff901f ITE borads/riscv/it8xxx2_evb: delete pwmleds node in dts
Delete pwmleds node in dts, because there isn't led on evb board.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-11-19 10:24:11 -06:00
Daniel DeGrasse
6608e68af5 boards: mimxrt11xx: Enabled FXOS8700 Accelerometer
Enables the FXOS8700 accelerometer included on the RT1160 EVK and RT1170
EVK.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-11-18 16:39:18 -06:00
Daniel DeGrasse
cb8c995235 boards: mimxrt11xx_evk: enable I2C
Enables LPI2C output on RT1160 and RT1170 EVK.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-11-18 16:39:18 -06:00
Gerard Marull-Paretas
db030c24b3 boards: arm: gd32f450i_eval: add initial support
Add initial support for the GD32F450I-EVAL board.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
809c35d430 dts: arm: gigadevice: organize dts files in folders
Create a folder for each of the series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
96966d180b soc: arm: gigadevice: gd32f403: simplify soc selection
There is no need to specify SoC suffixes, so simplify the selection.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
fcbb9476f8 soc: arm: gigadevice: use specific series for GD32F403
Despite the "F4" prefix, GD32F403 is an SoC with significant differences
compared to other F4 MCUs:

- It has a completely different HAL
- It has significant hardware differences, for example, the pinctrl
  mechanism uses AFIO (all others use AF)

The grouping principles applied to other similar vendors such as ST
can't be applied for GD32 due to these reasons, so the approach taken
here is to define series based on the used HAL. A different HAL likely
means that there are significant hardware differences between, e.g. F403
and F405. The vendor likely chose a confusing naming scheme, but we need
to deal with it.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
David Leach
a09ba37334 MXRT600: Fix secure/non-secure definition for FLEXSPI
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.

Changes include:

- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
2021-11-18 14:29:53 +01:00
Johann Fischer
b573d8df21 boards: remove Kconfig option CONFIG_USB_UART_CONSOLE
These boards try to configure CDC ACM UART as backend used
by the console driver. CONFIG_USB_UART_CONSOLE has no more
influence to console driver any and can be removed.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-11-18 14:29:18 +01:00
Maureen Helm
525fa76f4d boards: xtensa: Use a CMake variable to set the rimage target name
Removes hardcoded logic in the west signing script that translates
Zephyr board names to rimage target names. Instead, use a cached CMake
variable set at the board level to define its respective rimage target
name. This eliminates the need to modify the west signing script when
new SOF-supported boards are introduced to Zephyr.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-11-17 19:44:35 -05:00
Tim Lin
e29a15c0e3 ITE: drivers/serial: add the UART driver for the PM callback function
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.

note: pm_action_cb(old name: pm_control_fn)

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-11-16 21:23:42 -05:00
Alexandre Bourdiol
877379fba4 boards: arm: stm32: move "st,prescaler" to timers instead of pwm
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-11-16 09:55:30 -06:00
Jay Vasanth
70d4559fdf Microchip: MEC172x: eSPI driver
Updates to MEC172x eSPI driver to support ACPI shared
memory region and EC Host Command Subsystem through
ACPI_EC1 and Embedded Memory Interface (EMI).

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2021-11-16 10:43:42 +01:00
Immo Birnbaum
99b7e9d860 boards: arm: qemu_cortex_a9: change board's timing parameters
- Fix the system clock frequency: should be 111.1 MHz instead
of 100 MHz.
- Set ticks per second to 1000 for higher system clock precision.
- Set QEMU icount shift value to 3 so that one instruction gets
executed every 2^3 = 8 ns.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
2021-11-15 14:44:56 -05:00
Maureen Helm
836651b453 drivers: gpio: Refactor drivers to use shared init priority
Refactors all of the on-chip GPIO drivers to use a shared driver class
initialization priority configuration, CONFIG_GPIO_INIT_PRIORITY, to
allow configuring GPIO drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.

Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_DEFAULT or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.

Driver-specific options for off-chip I2C- or SPI-based GPIO drivers are
left intact because they often need to be initialized at a different
priority than on-chip GPIO drivers.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-11-15 14:38:55 -05:00
Anas Nashif
7424126060 boards: qemu_cortex_a9: use SUPPORTED_EMU_PLATFORMS
We moved from EMU_PLATFORM to SUPPORTED_EMU_PLATFORMS.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-11-14 10:11:06 -05:00
Filip Kokosinski
0851255258 boards: riscv: hifive1: add support for QEMU and Renode simulation
This commit adds required config files for Renode simulation and adds
missing QEMU_binary_suffix. It also adds flash and newlib tags to
ignore_tags, as flash chip is currently not provided by default in
Renode for FE310 and newlib does not fit into the available memory.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2021-11-12 21:33:42 -05:00
Filip Kokosinski
94428044e2 cmake: support multiple entries in board.cmake
Currently there is no way to support running a board on multiple
emulation platforms nor to choose a desired emulation platform for the
simulation to be run on. This commit introduces a new
SUPPORTED_EMU_PLATFORMS list, which defines available emulation
platforms for a given board.

Fixes #12375.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2021-11-12 21:33:42 -05:00
Ruibin Chang
e501c4a21a ITE boards/it8xxx2_evb: remove CONFIG_* not for every application
These drivers are no longer enabled for every application,
even hello_world. The right SoC-specific drivers are
enabled in applications that need them.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-11-12 10:25:47 -06:00
Ruibin Chang
4393f66ba2 ITE soc/riscv-ite/it8xxx2: move config to soc from board
Make config conditional and move to soc Kconfig.defconfig.series
from it8xxx2_evb_defconfig.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-11-12 10:25:47 -06:00
Sebastian Bøe
b39384f5df tf-m: Fix flashing of samples on nrf5340 and nrf9160 boards
Always flash the merged hex file.

This fixes flashing for samples. Before "west flash" only worked for
tests.

I don't know why this was not done from the get-go.

This also fixes builds that enables CONFIG_TFM_REGRESSION_NS, which will
use the tfm_ns application file instead of the zephyr application, and
will merge tfm_ns hex into the merged hex file. Otherwise the wrong
application hex file will be flashed.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2021-11-12 15:03:09 +01:00
Felipe Neves
b50cb2a537 drivers: counter: esp32: add support for esp32c3
to the unified esp32 counter driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-11 19:14:15 -05:00
Martí Bolívar
b330e3f374 boards: ubx_bmd345eval_nrf52840: shorten FEM settle times
Based on a report from Bob Recny, reducing the settling times doesn't
break anything.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-11-11 21:52:24 +01:00
Martí Bolívar
7ff74e0ab9 Bluetooth: controller: support FEMs via devicetree
A FEM in this case is an external Front-End Module. This is basically
a range booster with some extra amplification in the TX and RX paths.

This feature is supported for the Nordic open source controller. See
the changes to the ubx_bmd345eval_nrf52840 board for a quick summary
of what you have to do to take advantage of this.

(This patch doesn't actually remove the feature in the openisa HAL,
though, because that never implemented the required GPIO handling
routines.)

We are using the 'fem' property previously added to the
nordic,nrf-radio's devicetree binding, which points to the FEM that is
in use. If you have this property and the node it points to is
enabled, the controller subsystem respects it. Otherwise, FEM support
is disabled.

This obsoletes the following Kconfig options, which are now unused:

- CONFIG_BT_CTLR_GPIO_PA
- CONFIG_BT_CTLR_GPIO_PA_PIN
- CONFIG_BT_CTLR_GPIO_PA_POL_INV
- CONFIG_BT_CTLR_GPIO_PA_OFFSET

- CONFIG_BT_CTLR_GPIO_LNA
- CONFIG_BT_CTLR_GPIO_LNA_PIN
- CONFIG_BT_CTLR_GPIO_LNA_POL_INV
- CONFIG_BT_CTLR_GPIO_LNA_OFFSET

- CONFIG_BT_CTLR_FEM_NRF21540
- CONFIG_BT_CTLR_GPIO_PDN_PIN
- CONFIG_BT_CTLR_GPIO_PDN_POL_INV
- CONFIG_BT_CTLR_GPIO_CSN_PIN
- CONFIG_BT_CTLR_GPIO_CSN_POL_INV
- CONFIG_BT_CTLR_GPIO_PDN_CSN_OFFSET

The PA and LNA pins are now specified via fem-specific devicetree
properties in the FEM node:

- The "generic" PA/LNA case is handled with the ctx-gpios and
  crx-gpios properties of the generic-fem-two-ctrl-pins compatible,
  respectively.

- If the fem is an nRF21540, use the tx-en-gpios and rx-en-gpios
  properties instead (and also respectively). This allows us to specify
  FEM properties in a way that makes sense for the hardware datasheet,
  while still handling them in a uniform way within the controller.

We support this in the nRF5 HAL with a new radio_nrf5_fem.h
sub-header, which pulls in radio_nrf5_fem_generic.h or
radio_nrf5_fem_nrf21540.h depending on the fem node's compatible, if
one is defined. These in turn let us replace the implementation
routines in radio.c with DT equivalents.

Keep in-tree users and devicetree binding documentation up to date.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-11-11 21:52:24 +01:00
Jamie McCrae
6791aaec62 boards: arm: rm1xx_dvk: Add Laird Connectivity RM1xx development board
This is a development board which supports LoRa and Bluetooth Low
Energy functionality

Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
2021-11-10 09:05:07 -06:00
Francois Ramu
9d3ff71ae5 boards: stm32U585 disco kit enables the ADC1 peripheral
This PR enables the ADC1  for the b_u585i_iot02a disco kit
with input pin channel 15 on pb0.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-11-09 15:59:23 -06:00
Felipe Neves
857a188c76 drivers: watchdog: esp32: enabled esp32c3
support for the unified esp32 wdt driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-08 10:56:28 -05:00
Henrik Brix Andersen
5cd2b1ac46 boards: arm: waveshare_open103z: disable CAN bus tests
Disable CAN bus tests since can1 is disabled by default due to an IRQ
conflict with the USB controller.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-11-08 10:55:34 -05:00
Henrik Brix Andersen
c817a09b0a canbus: rename zephyr,can-primary chosen property to zephyr,canbus
Rename the Zephyr chosen property for specifying the default CAN bus
controller from "zephyr,can-primary" to "zephyr,canbus".

The "zephyr,can-primary" property name was selected in antipation of
adding support for redundant CAN networks, which we have yet to
add. Meanwhile, the "primary" term causes confusion for non-redundant
CAN bus configurations (and the "can" term doesn't match the name of the
Zephyr CAN bus subsystem).

The CAN in Automation (CiA) 302-6, which deals with CANopen network
redundancy, uses the terms "default interface" and "redundant
interface". If/when we add support for redundant CAN networks, the
"zephyr,canbus" chosen property can be supplemented with a
"zephyr,canbus-redundant" chosen property.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-11-07 09:05:39 -05:00
Marc Herbert
af1dedf89c boards: intel_adsp: add curly braces around log data in debug mode
This commit makes absolutely no change to the output unless debug is
manually turned on. Debug can be turned on with this other code change:

--- a/boards/xtensa/intel_adsp_cavs15/tools/logtool.py
+++ b/boards/xtensa/intel_adsp_cavs15/tools/logtool.py
@@ -45,7 +45,7 @@ def main():
         else:
             etrace = QEMU_ETRACE

-    l = Loglist(etrace)
+    l = Loglist(etrace, True)
     l.print()

Below are two examples of the new debug output. For instance the empty
and duplicate (due to a bug) slot [33] is now much more obvious:

};  {[31] : 1434444: ssp_set_config(),
};  {[32] : 1485591: ssp_set_config(),
};  {[33] : };  {[33] : 1539091: ssp_set_config(),

In this other example it is now much clearer that [7] misses a
`\n` newline:

};  {[6] : 858361: starting dma_trace_init_complete()
};  {[7] : dma_tr_...() ret=0[00000005] <inf> main};  {[8] : ipc_dma..()
};  {[9] : entering dma_trace_enable
};  {[10] : entering dma_trace_buffer_init()

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2021-11-07 05:34:06 -05:00
Marc Herbert
e4b453f5fc boards: intel_adsp: prefix "ADSP Reset" message with "invalid slot 0"
Unlike logtool.py, adsplog.py is not shielded from corrupted log data.
Lenghten the error message a bit and be more transparent about the
"invalid slot 0 => ADSP reset" assumption because it is usually but not
always true.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2021-11-07 05:34:06 -05:00
Marc Herbert
89bfee9975 boards: intel_adsp: suggest to unload driver when mmap fails in adsplog
When CONFIG_IO_STRICT_DEVMEM is set the logger script fails with a
cryptic `OSError: [Errno 22] Invalid argument`. Print a clue and
re-raise the OSError.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2021-11-07 05:34:06 -05:00
Marc Herbert
2fac69422c boards: intel_adsp: add comments explaining log IDs start from 1
The mismatch between the slot number and the sequence ("id") made me
suspect a bug for too long. Fix one related comment and add two more. No
code change.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2021-11-07 05:34:06 -05:00
Gerson Fernando Budke
d86b0de993 boards: arm: gd32f403z_eval: Enable gd32isp runner
Add support to gd32isp runner and update board documentation.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-11-07 05:20:50 -05:00
Gerson Fernando Budke
0de934b2a7 scripts: runner: Introduce gd32isp flash runner
Add GigaDevice ISP console flash runner.  This tool enable uses ROM
bootloader to flash devices using serial port.

The GD32_ISP_Console tool can be found at
  http://www.gd32mcu.com/download/down/document_id/175/path_type/1

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-11-07 05:20:50 -05:00
Sylvio Alves
ab91612a6d driver: esp32: I2C code refactoring
Use i2c_hal functions to enable support for
multiple SoCs.

Use DT compat to enable I2C from device
tree configuration

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-05 14:07:09 -04:00
Sylvio Alves
0931dd1d53 boards: faze: remove invalid defconfig
Removes invalid I2C defconfig in this board, as
config I2C_x is not implemented.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-05 14:07:09 -04:00
Sylvio Alves
3c34e156d9 boards: arduino: remove unused I2C config
Arduino Nano 33 board has undefined I2C_0 and I2C_1
configs. This removes it as I2C_TWIN kconfig already
handles it by its DTS file.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-05 14:07:09 -04:00
Henrik Brix Andersen
6cc536daa8 boards: riscv: neorv32: minor documentation improvements
Add a few minor improvements to the NEORV32 board documentation based on
community feedback.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-11-05 12:18:30 -05:00
Sylvio Alves
27e44acda1 clock: esp32: unify clock control for all espressif socs
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-04 15:21:26 -04:00
Francois Ramu
cd6adfe074 boards: arm: stm32 disco kit target board has USB-OTG instance
This commit enables the USB OTG full-speed instance (OTG)
on the target board b_u585i_iot02a from STMicroelectronics.
OTG is available on USB type-C connector (CN1).

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-11-04 10:25:17 -05:00
Maureen Helm
32b4950c61 drivers: eeprom: Refactor drivers to use shared init priority
Refactors all of the EEPROM drivers to use a shared driver class
initialization priority configuration, CONFIG_EEPROM_INIT_PRIORITY, to
allow configuring EEPROM drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.

The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The
exceptions are at2x and emul drivers which have dependencies on SPI,
I2C, or flash drivers and must therefore initialize later than the
default device priority.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-11-04 07:33:01 -04:00