In the function iwdg_stm32_install_timeout, the test on watchdog ready
was inverted. So, if 2 successive calls were made to this function, the
value of the prescaler or counter reload was not taken into account.
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
Instead of selecting appropriate HAS_HW_NRF_* options for particular
nRF SoCs (and simulated nRF52 target), set their values basing on
information from devicetree.
Correct also semantics of those options so that they are set only when
a corresponding DT node is enabled. This allows using them directly in
Kconfig dependencies of Zephyr drivers for nRF peripherals. Update
appropriately these dependencies.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Re-running the script that checks for the const qualifier missing on
struct device ISR's parameter.
The script also changes the parameter 'arg' to 'dev' when relevant.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Just use dev->name. This change follow same principles applied when
DEV_CFG and DEV_DATA macros were removed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
MCUX watchdog timer supports min window of 500ms. Increase maximum task
watchdog timeout window to 500ms by default, so that this sample can run
on iMX RT SOCs. Also update iMX RT watchdog driver to reject timeout
maximums under 500ms with a useful error message
Fixes#40153
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This corrects the following:
1. The priority of type cast is lower than member access. So don't need
the redundant parentheses.
2. The macro should be added to the parentheses.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Replace all get_dev_data()/get_dev_config() accessor utilities with
dev->data and dev->config.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add watchdog0 to support tests/drivers/watchdog/wdt_basic_api.
Solve tests code runtime error on it8xxx2_evb:
1.When run the wdt tests api, we shouldn't reduce the warning
timer time, so I add config WDT_ITE_REDUCE_WARNING_LEADING_TIME,
this config will be enabled only on platform EC.
2.Upper limit window timeouts can't be 0 when we install timeout.
3.Since we support wdt_it8xxx2_disable(), then we should support
flag WDT_OPT_PAUSE_HALTED_BY_DBG, too. Watchdog can be stopped
by IT8XXX2_WDT_EWDSCEN bit of ETWCTRL reg.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit is enabling the Debug support clock
like the stm32L0 or F0, the APB peripheral clock enable register 1
has a bit to clock DBGMCU before use.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is controlling the WWDG during the Stop mode in debug.
WWDG1 is frozen while the core is in Debug mode, setting the bit
of the DBGMCU APB1 peripheral freeze register (DBGMCU_APB1FZ2)
for the stm32MP1 soc devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is controlling the WWDG during the Stop mode in debug.
WWDG1 is frozen while the core is in Debug mode, setting the bit
of the DBGMCU APB3 peripheral freeze register (DBGMCU_APB3FZ1)
for the stm32H7 soc devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Added watchdog implementation which is using counter device
to implement watchdog driver API. Watchdog timeout is called from
counter interrupt context. Some counter implementations support
using ZLI interrupt level which can be use here as well. Watchdog
like this can be used along hardware watchdog to cover for its
limitations, i.e. Nordic watchdog resets unconditionally after
62uS after triggering watchdog interrupt. It is not enough time
to dump logging data.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Reduce interval of warning timer, so we can print more
warning messages (ex. MEPC, task ID...) before watchdog reset.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Instead of putting object files inside libzephyr.a,
simply build a separate static library as most other
driver types are doing this already.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add watchdog support to the mimxrt685 platform.
The mimxrt685 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt685 does not retain this memory through a
reset.
Signed-off-by: David Leach <david.leach@nxp.com>
Reboot functionality has nothing to do with PM, so move it out to the
subsys/os folder.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
TWDT0 is loaded with a new value and the counter restarts counting with
it by written RST bit in Timer Control register (T0CSR) to 1. Then, the
RST bit in T0CSR register is cleared automatically on the 2nd rising
edge of T0IN clock. Since TWCP is set to 1:32, the maximum time that RST
bit is unset is 32 * (1 / 32768) ~= 980us.
Polling this bit within a critical section in current npcx watchdog
driver isn't a good approach since it might block the other interrupts
need to service them in time. This CL introduces a timeout mechanism and
removes the critical section to improve this disadvantage. Consider the
clock tolerance, 2 ms is a suitable timeout value for RST bit. We also
remove polling for WD_RUN bit in T0CSR. Npcx watchdog needs serval LFCLK
(32k Hz) clocks to stop watchdog. 1 ms is long enough for the timeout
mechanism.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The source clock of the watchdog module is selected to the input of T0
timer, not output. Correct the drawing in case confusing the users.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
NPCX watchdog driver has a WDT_NPCX_DELAY_CYCLES for delay the watchdog
reset time after the watchdog timeout. For some systems, users would
like to use the watchdog timeout ISR but don't reset the chip
immediately. Let the system have the final chance to ongoing the system
before the real hardware reset time. Removing the watchdog reset
waiting loop in ISR lets users decide whether wait for watchdog reset
by themself.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
As older series supported only 4 different prescaler values the
highest prescaler value was hardcoded. Newer series support 8
programmable prescaler values, therefore take the allowed values from
ll_wwdg header file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Series STM32G0, STM32G4, STM32H7, STM32L5, STM32WB, STM32WL have
a newer wwdg ip and store the prescaler value not in bits[8:7],
but bits bits[13:11], use the definitions from ll to account for that.
Remove IS_WWDG_PRESCALER, this is not required as the prescaler
is not calculated, but known valid prescaler values are tested until a
valid counter is found.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The comparison was inverted before so configuring a valid window
providing min and max was not possible.
Now the comparison is corrected and only done if the watchdog is used in
windowed mode.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Register T0CSR bit 4 is WDRST_STS which is used to check whether the
chip has watchdog reset from the last power-up or vcc1_rst. WDRST_STS
hardware is design to write one clear. For the original
read-modify-write, it will reset the WDRST_STS unexpected. Add a mask
to avoid it.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
In function wwdg_stm32_init, return value of clock_control_on
was not checked.
This is reported as an issue by coverity (CID 219600).
Fix this.
Fixes#33067
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rather than Kconfig vendor symbols, select stm32 watchdog using
compatible.
So user only has to enable the requested node and set
CONFIG_WATCHDOG=y.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fix the timeout computation to provide more accurate timeouts
versus requested timeout.
Additionally, the error margin is reworked in order to:
- be relative to the application requested timeout (10% tolerance)
- exclude timeouts inferior to application request
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
