drivers: watchdog: npcx: mask the WDRST_STS when accessing T0CSR
Register T0CSR bit 4 is WDRST_STS which is used to check whether the chip has watchdog reset from the last power-up or vcc1_rst. WDRST_STS hardware is design to write one clear. For the original read-modify-write, it will reset the WDRST_STS unexpected. Add a mask to avoid it. Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
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1 changed files with 4 additions and 3 deletions
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@ -88,7 +88,8 @@ static inline void wdt_t0out_reload(const struct device *dev)
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key = irq_lock();
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/* Reload and restart T0 timer */
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inst->T0CSR |= BIT(NPCX_T0CSR_RST);
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inst->T0CSR = (inst->T0CSR & ~BIT(NPCX_T0CSR_WDRST_STS)) |
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BIT(NPCX_T0CSR_RST);
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/* Wait for timer is loaded and restart */
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while (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_RST))
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;
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@ -312,8 +313,8 @@ static int wdt_npcx_init(const struct device *dev)
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inst->TWCFG = BIT(NPCX_TWCFG_WDSDME) | BIT(NPCX_TWCFG_WDCT0I);
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/* Disable early touch functionality */
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inst->T0CSR |= BIT(NPCX_T0CSR_TESDIS);
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inst->T0CSR = (inst->T0CSR & ~BIT(NPCX_T0CSR_WDRST_STS)) |
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BIT(NPCX_T0CSR_TESDIS);
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/*
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* Plan clock frequency of T0 timer and watchdog timer as below:
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* - T0 Timer freq is LFCLK/32 Hz
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