Add DT definitions for the RAK3172 LoRaWAN module, based on
STM32WLE5.
Ref. https://docs.rakwireless.com/product-categories/wisduo/
rak3172-module/low-level-development/
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
These devices have an architecturally fixed 13 MHz clock device. But
thankfully you can put a default into a DTS binding so we don't have
to repeat it for all of them.
Signed-off-by: Andy Ross <andyross@google.com>
In order for the driver to be compliant with the timing sequence
diagrams presented in the reference manual, the MCU has to wait
for some additional period of time while setting both the rs and rw
lines.
Signed-off-by: Jan Kuliga <jtkuliga@gmail.com>
Express delay values in nanoseconds. Set the default delay time values
as specified in the HD44780 reference manual.
Signed-off-by: Jan Kuliga <jtkuliga@gmail.com>
Separate the current driver for the FPGA iCE40 into two different ones.
One implements only the SPI load mode, the other one only the GPIO
bitbang mode.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The GECKO_PIN() macro does not do anything except pass the
argument through unaltered. It only serves to make DeviceTree
files more verbose. It was inconsistently used, make the .dts
files consistent by never using it.
The DBUS pinctrl driver doesn't use the port or location macros
from the gpio_gecko.h header. The pin number macro is the only
other thing defined in this header. Stop including the header on
Series 2 based boards.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Swap from silabs,gecko-pinctrl to silabs,dbus-pinctrl for all boards
with Series 2 SoCs. Explicitly declare pin properties as part of
pinctrl pinout configuration.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Silicon Labs Series 2 and newer devices do alternate function
configuration fundamentally differently from Series 0 and 1. Pin routing
is done in a centralized fashion in the GPIO peripheral, as opposed to
having ROUTE registers in every peripheral. The concept of alternate
function location numbers also does not exist, functions are directly
assigned to GPIOs by their port and pin number.
This commit adds a new pinctrl driver for devices that use DBUS. It fully
makes use of pinctrl design principles as outlined in the Zephyr
documentation. The previous driver hard-codes pin properties such as filter
and pull-up/down in the driver itself, while the new driver leaves this up
to the user as configurable DeviceTree properties. The previous driver has
hard-coded support for UART, SPI and I2C, while the new driver has generic
support for all DBUS signals.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Flash node should not be under the peripheral bus, it is not a
peripheral. The base address of the flash was getting set correctly by
accident due to the fmu node mapping it out of the range of the
peripheral node by coincidence.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add RTIO async and RTIO stream functionalities that enables,
among all the other things, the sensor data streaming from FIFO.
RTIO stream is using both SENSOR_TRIG_FIFO_WATERMARK and
SENSOR_TRIG_FIFO_FULL triggers. The decoder currently only supports
following FIFO tags:
- LSM6DSV16X_XL_NC_TAG
- LSM6DSV16X_GY_NC_TAG
- LSM6DSV16X_TEMP_NC_TAG
Following FIFO parameters has to be defined in device tree to
correctly stream sensor data:
- fifo-watermark (defaults to 32)
- accel-fifo-batch-rate (defaults to LSM6DSV16X_DT_XL_NOT_BATCHED)
- gyro-fifo-batch-rate (defaults to LSM6DSV16X_DT_GY_NOT_BATCHED)
- temp-fifo-batch-rate (defaults to LSM6DSV16X_DT_TEMP_NOT_BATCHED)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
In most implements, the msip base address is 0x2000000. But the address
is not fixed in all boards.
Signed-off-by: Yang Jialong <yangjialong@vcore.com>
Convert the eDMA compat to prop version for NXP S32Z2 SoC
that was missed in commit b070da7c33.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Since the label property from base.yaml is no longer deprecated, no need
to require to explicitly block it.
The only affected bindings seem to be these test bindings.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Label property is described in DT spec and does not need to be
deprecated in base.yaml anymore. It was originally deprecated to
discourage what was previously the most common use case of labels in
zephyr which was the old device_get_binding, which was rightfully
removed. However, labels do have a purpose as described in DT spec of
providing a human readable string to software to describe the device,
which there is some use for.
The description of a label should be given in the device binding, as
stated in DT spec.
Label properties should be of type string.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add devicetree node for code RAM, code RAM can be accessed
over AIXM bus or AXIF bus. Code access via AXIF interface
provides the best optimal performance
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add `idle` and `s2ram` power states for nRF54H20 cpuapp and cpurad.
Also the substate `idle_cache_disable` added.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Introduce etrbuffer in the tddconf bindings to support flexible
placement in the memory map.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
This commit adds the pfic interrupt controller driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the usart driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the systick driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the clock driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the pinctrl driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the dtsi and bindings for the WCH CH32V003 which is a
32-bit general-purpose RISC-V MCU.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
- Add SPI driver support for RA
- RA2A1 not support slave select keeping level so disable it
in Kconfig
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Use a string for the mipi-mode property over an integer value, as this
significantly improves the readability of the MIPI DBI device binding.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP LCDIC peripheral contains two internal timers, with configurable
periods. These times are used to determine delays within the peripheral,
such as the reset and tearing enable signal delays. Allow these periods
to be set within the devicetree for the peripheral.
Raise the period where required for display drivers that need a value
other than the reset setting
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Extend tca954x (tca9546a, tca9548a) driver to support tca9544a i2c MUX.
(different bitmask and flag for enable bit in register)
Signed-off-by: Florian Weber <Florian.Weber@live.de>
The NXP PORT pinmuxing peripheral is reused across the MCX, S32, and
Kinetis lines. Rename the compatible from the family-specific
nxp,kinetis-pinctrl to a more generic nxp,port-pinctrl to reflect the
actual name for the IP block used within reference manuals.
Update the NXP HAL revision to include a change to use the new Kconfig
name for the PORT pinctrl driver
Update the MAINTAINERS.yml path, as there are no longer any NXP drivers
matching the string "drivers/*/*kinetis*
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
* Replace copies of fixed-partitions nodes in related boards by
referencing the apropriate partition table from the available list.
* For better reference the `partitions_*.dtsi` file has boot offset,
purpose and the flash size encoded in the file name. Default flash size
is considered to be 4MB.
* Added the flash size node for the boards which are not based on the
module.
* Removed flash size registry from the esp32.*common.dtsi
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Split and fix the total SRAM size for STM32L4Px/L4Qx/L4Rx/L4Sx
device. Those MCUs with up to 640 Kbytes SRAM:
This is 640KB for the STM32L4Rxxx and STM32L4Sxxx devices :
• 192 Kbytes SRAM1 + 64 Kbytes SRAM2 + 384 Kbytes SRAM3
This is 320KB for the STM32L4P5xx and STM32L4Q5xx devices :
• 128 Kbytes SRAM1 + 64 Kbytes SRAM2 + 128 Kbytes SRAM3
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Split and fix the total SRAM size for STM32L47x/L48x/L49x/L4Ax
device. Those MCUs with up to 320 Kbytes SRAM:
• 96 Kbytes SRAM1 and 32 Kbyte SRAM2 on STM32L47x/L48x.
• 256 Kbyte SRAM1 and 64 Kbyte SRAM2 on STM32L49x/L4Ax
The sram0 node at address 0x20000000 and sram1 at address 0x10000000
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace the DT_INST_PROP_OR statements with defaults
in the devicetree binding of the iCE40.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
These two new ICs are variants of the nRF54L15 with different memory
sizes:
- nRF54L05: 500KB RRAM, 96KB RAM
- nRF54L10: 1022KB RRAM, 192KB RAM
- nRF54L15: 1524KB RRAM, 256KB RAM
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
