Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the I2C peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the ADC peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the UART/USART/LPUART
peripherals. Changes performed using the following Python script run
from the repository root:
```
from pathlib import Path
import re
for fpath in Path(".").glob("boards/arm/**/*.dts"):
lines = open(fpath).readlines()
is_stm32 = False
for line in lines:
if "stm32" in line:
is_stm32 = True
break
if not is_stm32:
continue
with open(fpath, "w") as f:
for line in lines:
f.write(line)
m = re.match(r"(\s+)pinctrl-0.*us?art.*", line)
if m:
f.write(m.group(1) + "pinctrl-names = \"default\";\n")
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable the pin control driver on all STM32 based boards. The following
script has been used to do this task:
```
from pathlib import Path
import re
for fpath in Path(".").glob("boards/arm/**/*_defconfig"):
lines = open(fpath).readlines()
is_stm32 = False
for line in lines:
if "CONFIG_SOC_SERIES_STM32" in line:
is_stm32 = True
break
if not is_stm32:
continue
lines += ["\n", "# enable pin controller\n", "CONFIG_PINCTRL=y\n"]
with open(fpath, "w") as f:
f.writelines(lines)
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The qemu arm64 virt machine PCIe controller config space needs a
64bit adressing, so switch the entire qemu-virt-a53 and
qemu_cortex_a53 board dts to address-cells & size-cells to 2
to accommodate for 64bit addresses.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add gpio to supported list in native_posix boards so that the gpio tests
with the gpio_emul will run in twister.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
With -Wdouble-promotion added to the warning base, posix gives warnings
when compiled with this on. Cast the constants to long doubles, and the
print %f variable to a double.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
Failed to flash blinky example to stock nucleo_wl55jc due to default
application entering low power mode using WFI. To connect to a sleeping
stm32wl55 a system reset is required.
Signed-off-by: Jelle De Vleeschouwer <jelledevleeschouwer@gmail.com>
* With existence of Adafruit Qt Py boards, and upcoming wireless
Xiao from Seeeduino, define nexus node and peripheral node
labels for use with shields that accept any Xiao format board.
* Adds `&xiao_d`, `&xiao_spi`, `&xiao_i2c` and `&xiao_serial` generic
node labels.
* Add new 'seeed-xioa-header.yaml` to document new nexus node.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
This sets the commonly used serial port alias for blackmagicprobe, as
well as the flag to reset on connect, so that flashing works in low
power.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add the power state configs so that the board can be used with suspend
to idle out of the box. This is the same config as the one in
nucleo_wl55jc.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The TFM build directory path is hardcoded in many places.
In order to support out-of-tree secure partitions the output path
has to be known in potentially out-of-tree build scripts.
This could potentially break out-of-tree build scripts if the
location of the build directory was changed.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
For reStructuredText, continuing text in a numbered list must be aligned
to the first line.
These lines are searched by the following regex:
ag '#\. .*\n[^ #\n]' **/*.rst
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Despite the "F4" prefix, GD32F403 is an SoC with significant differences
compared to other F4 MCUs:
- It has a completely different HAL
- It has significant hardware differences, for example, the pinctrl
mechanism uses AFIO (all others use AF)
The grouping principles applied to other similar vendors such as ST
can't be applied for GD32 due to these reasons, so the approach taken
here is to define series based on the used HAL. A different HAL likely
means that there are significant hardware differences between, e.g. F403
and F405. The vendor likely chose a confusing naming scheme, but we need
to deal with it.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.
Changes include:
- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
These boards try to configure CDC ACM UART as backend used
by the console driver. CONFIG_USB_UART_CONSOLE has no more
influence to console driver any and can be removed.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Removes hardcoded logic in the west signing script that translates
Zephyr board names to rimage target names. Instead, use a cached CMake
variable set at the board level to define its respective rimage target
name. This eliminates the need to modify the west signing script when
new SOF-supported boards are introduced to Zephyr.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.
note: pm_action_cb(old name: pm_control_fn)
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Updates to MEC172x eSPI driver to support ACPI shared
memory region and EC Host Command Subsystem through
ACPI_EC1 and Embedded Memory Interface (EMI).
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
- Fix the system clock frequency: should be 111.1 MHz instead
of 100 MHz.
- Set ticks per second to 1000 for higher system clock precision.
- Set QEMU icount shift value to 3 so that one instruction gets
executed every 2^3 = 8 ns.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Refactors all of the on-chip GPIO drivers to use a shared driver class
initialization priority configuration, CONFIG_GPIO_INIT_PRIORITY, to
allow configuring GPIO drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_DEFAULT or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
Driver-specific options for off-chip I2C- or SPI-based GPIO drivers are
left intact because they often need to be initialized at a different
priority than on-chip GPIO drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
This commit adds required config files for Renode simulation and adds
missing QEMU_binary_suffix. It also adds flash and newlib tags to
ignore_tags, as flash chip is currently not provided by default in
Renode for FE310 and newlib does not fit into the available memory.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Currently there is no way to support running a board on multiple
emulation platforms nor to choose a desired emulation platform for the
simulation to be run on. This commit introduces a new
SUPPORTED_EMU_PLATFORMS list, which defines available emulation
platforms for a given board.
Fixes#12375.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
These drivers are no longer enabled for every application,
even hello_world. The right SoC-specific drivers are
enabled in applications that need them.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Always flash the merged hex file.
This fixes flashing for samples. Before "west flash" only worked for
tests.
I don't know why this was not done from the get-go.
This also fixes builds that enables CONFIG_TFM_REGRESSION_NS, which will
use the tfm_ns application file instead of the zephyr application, and
will merge tfm_ns hex into the merged hex file. Otherwise the wrong
application hex file will be flashed.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
