Commit graph

58183 commits

Author SHA1 Message Date
Erwan Gouriou
90b0e92540 drivers/usb/device: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Additionally, rename usb_pinctrl to usb_pcfg to better fit
new pinctrl API.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
ad4e5d85fe boards: arm: stm32: add pinctrl state name for USB peripheral
Add the pinctrl state name (default) for the USB peripherals.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
8bd410a589 drivers/spi: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
1c66ccdac3 boards: arm: stm32: add pinctrl state name for SPI peripheral
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
ab893d5fef drivers/memc: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
ab306b34db boards: arm: stm32: add pinctrl state name for FMC peripheral
Add the pinctrl state name (default) for the FMC peripherals.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
79943f647f drivers/i2s: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
895e1ddb69 boards: arm: stm32: add pinctrl state name for I2S peripheral
Add the pinctrl state name (default) for the I2S peripherals.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
f21de9dfe6 drivers/i2c: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
dfbaa4149d boards: arm: stm32: add pinctrl state name for I2C peripheral
Add the pinctrl state name (default) for the I2C peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
ff55408ad0 boards: nucleo_f446ze: Remove QSPI node definition
There's no QSPI peripheral device available on this board.
Remove node definition.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
cec2cb69dd drivers/flash: qspi stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
ed27d71eba boards: arm: stm32: add pinctrl state name for QSPI peripheral
Add the pinctrl state name (default) for the QSPI peripherals.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
18ae799b73 drivers/ethernet: dwmac_stm32h7x: use new pinctrl API
Use the new pinctrl API to configure pins.

Additionally, rename eth0_pins to eth0_pcfg to better fit
new pinctrl API.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
87438e4587 drivers/ethernet: stm32_hal: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
ed5ea6022a boards: arm: stm32: add pinctrl state name for ethernet peripheral
Add the pinctrl state name (default) for the ethernet peripherals.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
d55905b2f7 drivers/disk: sdmmc: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
3dde131cb8 boards: arm: stm32: add pinctrl state name for SDMMC peripheral
Add the pinctrl state name (default) for the SDMMC peripherals.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
956afc3a08 drivers/dac: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
8b0c2ca290 boards: arm: stm32: add pinctrl state name for DAC peripheral
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
65d222b0ab drivers/fdcan: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
274e83409d boards: arm: stm32: add pinctrl state name for FDCAN peripheral
Add the pinctrl state name (default) for the FDCAN peripherals.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
337c9b96e9 drivers/can: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
da3fb8faa5 boards: arm: stm32: add pinctrl state name for CAN peripheral
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
93956b2073 drivers/adc: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Erwan Gouriou
36204c3c80 boards: arm: stm32: add pinctrl state name for ADC peripheral
Add the pinctrl state name (default) for the ADC peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-26 11:36:42 +01:00
Gerard Marull-Paretas
21a271962c drivers: serial: stm32: use new pinctrl API
Use the new pinctrl API to configure pins.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 11:36:42 +01:00
Gerard Marull-Paretas
4b9c3d7134 boards: arm: stm32: add pinctrl state name for UART peripheral
Add the pinctrl state name (default) for the UART/USART/LPUART
peripherals. Changes performed using the following Python script run
from the repository root:

```
from pathlib import Path
import re

for fpath in Path(".").glob("boards/arm/**/*.dts"):
    lines = open(fpath).readlines()

    is_stm32 = False
    for line in lines:
        if "stm32" in line:
            is_stm32 = True
            break

    if not is_stm32:
        continue

    with open(fpath, "w") as f:
        for line in lines:
            f.write(line)

            m = re.match(r"(\s+)pinctrl-0.*us?art.*", line)
            if m:
                f.write(m.group(1) + "pinctrl-names = \"default\";\n")
```

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 11:36:42 +01:00
Gerard Marull-Paretas
070e2f0782 boards: arm: stm32: enable pinctrl driver
Enable the pin control driver on all STM32 based boards. The following
script has been used to do this task:

```
from pathlib import Path
import re

for fpath in Path(".").glob("boards/arm/**/*_defconfig"):
    lines = open(fpath).readlines()

    is_stm32 = False
    for line in lines:
        if "CONFIG_SOC_SERIES_STM32" in line:
            is_stm32 = True
            break

    if not is_stm32:
        continue

    lines += ["\n", "# enable pin controller\n", "CONFIG_PINCTRL=y\n"]

    with open(fpath, "w") as f:
        f.writelines(lines)
```

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 11:36:42 +01:00
Gerard Marull-Paretas
9c10e1e988 drivers: pinctrl: stm32: initial version
Add initial version for STM32 pinctrl driver. Driver has been written
re-using many of the already existing parts in
drivers/pinmux/pinmux_stm32.c.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 11:36:42 +01:00
Gerard Marull-Paretas
b5d6aa29e8 pm: device: move Z_DEVICE_PM_DEFINE_PM_SLOT to pm
The macro has been moved to the pm/device.h header, being now called by
the Z_PM_DEVICE_DEFINE macro. This means that a slot will only be
created if the device uses PM, thus reducing memory usage.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 10:42:55 +01:00
Krzysztof Chruscinski
9886bdc0c8 drivers: pwm: pwm_nrf5_sw: Use runtime resources allocation
Use nrfx_gpiote and nrfx_ppi allocators to allocate channels
at runtime instead of fixed, device-tree based allocation which
is harder to maintain.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-11-26 09:31:54 +01:00
NingX Zhao
5287ce8ff0 poll: modify the function z_vrfy_k_poll
Removing the 'U' to avoid the type of num_events changed.
And make sure it is meaningful Z_SYSCALL_VERIFY micro.

Fixed #40614

Signed-off-by: NingX Zhao <ningx.zhao@intel.com>
2021-11-25 18:23:51 -05:00
Torsten Rasmussen
d2cdee5b25 cmake: cleanup all intermediate build files.
Fixes: #40643

The intermediate build files produced by the build system may be very
large.

The last pre-built image has been removed when
`CONFIG_CLEANUP_INTERMEDIATE_FILES=y` but when the gen_handles.py call
was moved from the last pre-built image to the first image, the first
image increased in size.
But first image was never cleaned after build.

This commit updates the behaviour so that all intermediate images are
removed when `CONFIG_CLEANUP_INTERMEDIATE_FILES=y` and not only the
final image.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-11-25 18:22:32 -05:00
Neil Armstrong
f8f2936dba pcie: add initial controller support
This adds :
- Generic PCIe Controller layer implementing the current PCIe API
- Generic PCIe Controller in ECAM mode driver

The Generic PCIe Controller layer provides:
- Configuration space read/write
- single bus endpoint enumerations
- Endpoint I/O, MEM & MEM64 BARs allocation
- Endpoint I/O, MEM & MEM64 BARs get & translation for drivers

The Generic PCIe Controller in ECAM mode driver provides:
- Raw DT RANGES properties into usable PCIe regions
- Configuration space read/write into ECAM config space
- PCIe regions allocation & translation

The limitations are:
- No support for PCIe prefetchable regions
- No support for PCIe bus configuration (only bus0 is supported)
- No support for multiple controllers (no domain-id in BDF)

Support has been designed to initially support Root Complexes with
Root Complex Integrated Endpoint, which was designed for Embedded
Systems with internal-only PCIe Endpoints on bus 0.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-25 18:37:15 +01:00
Neil Armstrong
c714368691 pcie: add PCIe Controller API
This adds a generic PCIe Controller driver API providing the
necessary callbacks & config structure to handle the PCIe
config space and BAR regions handling.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-25 18:37:15 +01:00
Neil Armstrong
3f68124c56 bindings: pcie: add pci-host-ecam-generic bindings
Add bindings for a generic PCIe Controller in ECAM mode.

ECAM stands for PCI Express Enhanced Configuration Access Mechanism
where the PCIe config space is flat memory-mapped.

An optional msi-parent phandle is added to link to an optional
MSI/MSI-X Interrupt Message Translation HW component.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-25 18:37:15 +01:00
Neil Armstrong
4a4272cefc doc: devicetree: add PCIe controller chosen property
Add a new chosen property to indentify the main PCIe Controller
node of the system.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-25 18:37:15 +01:00
Neil Armstrong
e636f149aa dts: arm64: qemu-virt: switch to 64bit addressing in DT
The qemu arm64 virt machine PCIe controller config space needs a
64bit adressing, so switch the entire qemu-virt-a53 and
qemu_cortex_a53 board dts to address-cells & size-cells to 2
to accommodate for 64bit addresses.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-25 18:37:15 +01:00
Robert Lubos
e6d619ea3d net: l2: ieee802154: Fix packed structure warning
`struct ieee802154_mpdu` access generates warnings related to unaligned
access to packed structure member. The structure itself however does not
need to be packed, since it is not mapped directly into the frame
buffer, but rather contains pointers to the structures representing
corresponding header regions in the frame. Those structures are
correctly defined as packed.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-11-25 10:46:35 -05:00
Robert Lubos
6dbd5c7876 net: icmpv6: Remove in6_addr from packed structs
Replace unpacked in6_addr structures with raw buffers in packed icmpv6
structs, to prevent compiler warnings about unaligned access.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-11-25 10:46:35 -05:00
Robert Lubos
666e9f80d6 net: ipv6: Remove in6_addr from packed net_ipv6_hdr struct
Replace unpacked in6_addr structures with raw buffers in net_ipv6_hdr
struct, to prevent compiler warnings about unaligned access.

Remove __packed parameter from `struct net_6lo_context` since the
structure isn't really serialized.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-11-25 10:46:35 -05:00
Robert Lubos
064200b420 net: ipv4: Remove in_addr from packed net_ipv4_hdr struct
Replace unpacked in_addr structures with raw buffers in net_ipv4_hdr
struct, to prevent compiler warnings about unaligned access.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-11-25 10:46:35 -05:00
Robert Lubos
bbdeef4ac4 net: arp: Remove in_addr/in6_addr from packed net_arp_hdr struct
Replace unpacked in_addr/in6_addr structures with raw buffers in
net_arp_hdr struct, to prevent compiler warnings about unaligned
access.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-11-25 10:46:35 -05:00
Robert Lubos
0da228c57c net: ip: Verify that in_addr/in6_addr struct sizes are correct
Make sure that in_addr/in6_addr structure size match the respective
binary IP address size with BUILD_ASSERT.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2021-11-25 10:46:35 -05:00
Andries Kruithof
984ebd519a Bluetooth: controller: remove obsolete defines
The define for PDU_AC_LL_SIZE_EXTRA was removed in main, but not in
the topic-branch. The merge of topic/branch erroneously reintroduced
this define, so it needs to be removed

Signed-off-by: Andries Kruithof <Andries.Kruithof@nordicsemi.no>
2021-11-25 10:46:08 -05:00
Andries Kruithof
2e2900f1bb Bluetooth: controller: revert erroneous deletion
During work on the new LLCP the assignment to
phy_aux_flags_rx was by accident deleted.
This reverts that deletion

Signed-off-by: Andries Kruithof <Andries.Kruithof@nordicsemi.no>
2021-11-25 10:45:50 -05:00
Maik Vermeulen
f2ca6a8c22 net: lwm2m: Add observe callback for observe and notification events
Added an observe callback so that the application can register to
receive events like observer added/deleted, and notification acked/
timed out. The notifications can be traced back to the exact data
contained within them by use of the user_data pointer.

Fixes #38531.

Signed-off-by: Maik Vermeulen <maik.vermeulen@innotractor.com>
2021-11-25 10:45:36 -05:00
Ilhan Ates
917adaea77 Bluetooth: host: Fix notify multiple issue
When multiple notify feature is enabled, notifications are pushed
twice. Host sends multiple notify with BT_ATT_OP_NOTIFY_MULT and
then continues to send regular notification with BT_ATT_OP_NOTIFY.

Fixes: https://github.com/zephyrproject-rtos/zephyr/issues/40546

Signed-off-by: Ilhan Ates <ilhan.ates@nordicsemi.no>
2021-11-25 10:44:54 -05:00
Andries Kruithof
a60f0ac7a4 tests: edtt: re-enable HCI tests
HCI tests HCI/DSU/BV-05-C and HCI/GEV/BV-01-C fail when
compiling with debug optimisations turned on.
Therefor revert to not compiling with debug optimisations.

Signed-off-by: Andries Kruithof <Andries.Kruithof@nordicsemi.no>
2021-11-25 10:44:34 -05:00