Adds a dtsi file for the STM32F401XD family of devices. These devices
are closely related to the STM32F401XE family of devices but with a
reduced flash memory from 512kB to 384kB.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
Add Bouffalo Lab serial driver. The driver uses pinctrl to configure
pins and have power management capabilities.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add it515xx analog to digital converter driver which supports 8 channels
ch0 ~ ch7 and 12-bit resolution.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
When GPIO17 or 16 is used as an external REF_CLK signal, the output is
enabled in eth_esp32.c This was added in PR number #65759 and then refined
in PR #74442. However this does not work for PHYs which need the REF_CLK
for MDIO communication, such as LAN8720A. In such cases phy_mii driver
tries to get the ID of such a PHY before REF_CLK is present. Therefore
in this PR I propose to move REF_CLK initialization from eth_esp32.c to
mdio_esp32.c which gets initialized before PHY and ETH.
Signed-off-by: Łukasz Iwaszkiewicz <lukasz.iwaszkiewicz@gmail.com>
Switches back to equal sized partitions, this fixes an issue
whereby the number of overhead sectors for a swap mode was
incorrectly listed as 2 when it should have been 1, and also
allows using any swap mode. This means that when using swap
using mode, 1 sector in the secondary partition will be unusable,
and when using swap using offset, 1 sector in the primary
partition will be unusable
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Enhanced uart-controller.yaml to expand parity type support,
now including 'mark' and 'space' options.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Introduce NXP NCNano driver using MIPI DBI class. This peripheral
supports 8080 and 6800 mode. The driver also supports used with
nxp,mipi_dsi_2l driver, for the panel with DPHY bus, such as g1120b0mipi.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Update nxp,dcnano-lcdif to support IP change on RT700. There are extra
registers need to be configured for the lcdif on RT700. Add new binding
item "version" to tell which version of the IP the SoC has.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
To split bus support into separate files. This patch does not introduce
any functionality, but rather precedes a patch introducing I2C bus
support.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
In STM32N6, AXISRAM1 is next to the 400kB FLEXRAM.
By default, the FLEXRAM is configured to extend the AXISRAM1 which put
its total size to 1024kB.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the default kernel clock (HCLK5) for the XSPI instances instead of the
peripheral clock which may not be enabled at all.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Errata sheet ES0620 indicates that STM32N6 APB prescalers cannot be
modified.
Fixes the value of all APB prescalers to 1 (default value).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Added driver for the PAJ7620 gesture sensor. For now,
just added basic gesture mode, although sensor also
has other modes (proximity and cursor modes).
Signed-off-by: Paul Timke Contreras <ptimkec@live.com>
The driver no longer requires a backlight enable GPIO pin to be defined,
which allows compatibility with displays that do not provide such a pin.
Signed-off-by: Isaev Denis <anelderlyfox@yahoo.com>
The device tree entry for cva6 is currently missing a device tree node
for the mtime and mtimecmp registers in the core-local interrupt
controllers.
This causes the RISC-V machine timer driver not to be built, causing
build failures as the system clock is missing.
This commit rectifies this by adding the corresponding device tree
entry.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The flash size is the second part (size) of the first reg value, not the
first part (address) of a nonexistent second reg value.
Based-on-patch-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
This adds a v1.0 support dts flag for devices. This also makes it so it
doesn't try to send a GETCAPS (GETHDRCAP) ccc if this flag is set and it
doesn't support any HDR modes.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The current configuration allocate 476kB (672 − 196) to the NWP. This
configuration is only required with offloaded network stack
(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD).
Since this parameter is not set by default, increase memory allocated to
Zephyr.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
- 196kB
- 256kB
- 320kB
Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Some instances of DMA (dma0) can use the normal sram to store their
descriptors. In this case, it makes sense to allow the linker to
allocate the memory rather than tweaking the memory layout.
So, if the attribute silabs,sram-region is not defined, use a statically
allocated buffer.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Memory areas for DMA descriptors are shared with the DMA hardware block.
There area should be cached by the CPU.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.
Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.
Then, with this new implementation, the memory mapping is easier to
understand for the reader.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add support for SPI to cc23x0 SoC. Only controller mode is implemented.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
