<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> was included because some CMSIS helpers (__DMB/__ISB) were
needed. In ARM SoCs, inclusion of CMSIS headers depends mainly on how
HALs decide to do it, being usually an inefficient and fragile include
chain. Note that on ARM64 we're in a better position, as those are
defined in-tree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add a new selectable Kconfig option to decide wether the device driver
is a MMIO device or not. Previous to this patch, the decision was maded
based on the existence of a definition in <soc.h>. The design was
fragile, as code compiled anyway if the definition was not present.
All platforms/boards that had the definition in <soc.h> select the
Kconfig option in their respective defconfig files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Deep Sleep mode stops SMB module clocks which could interrupt ongoing
I2C transactions, so have the I2C driver acquire a PM lock at the
beginning of a transaction and release it at the end in order to ensure
the module remains active.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Remove unconditional write to PCA95xx output registers in setup_pin_dir,
and only write to output registers if selected pin is configured as
an output.
Fixes#45774
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch adds DTS properties for using wake-up mode
and the autosleep function to the ADXL362 driver.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
As per XMCLib documentation we need to check that data has been received
before reading the buffers.
Fixes test_uart_poll_in test in tests/drivers/uart/uart_basic_api.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Casting to uint16_t* can cause an unaligned usage fault when c is not
aligned to 2 bytes and can unintentionally overwrite data when c has a 1
byte memory size. Also there's no need to cast to uint16_t* because
returned words are 8-bit characaters as setup in the configuration.
Fixes the following usage fault error in tests/drivers/uart/uart_basic_api:
START - test_uart_poll_in
Please send characters to serial console
E: ***** USAGE FAULT *****
E: Unaligned memory access
E: r0/a1: 0x00000000 r1/a2: 0x2000078f r2/a3: 0x0c00453c
E: r3/a4: 0x00000000 r12/ip: 0x00000000 r14/lr: 0x0c003de5
E: xpsr: 0x41000000
E: Faulting instruction address (r15/pc): 0x0c003de4
E: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0
E: Current thread: 0x20000118 (unknown)
E: Halting system
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The CPU in Aspeed AST10x0 SOC is a ARM Cortex-M4 which doesn't internal
cache memory. Aspeed implements an integrated system level cache to
accelerate instruction and data memory accesses.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Add a pseudo device diver with device tree bindings for coredump.
The device tree bindings exposes memory address/size values to be
included in any dump. And the driver exposes an API to add/remove
dump memory regions at runtime.
Signed-off-by: Mark Holden <mholden@fb.com>
This commit aligns SPIM shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
This commit aligns UARTE shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
The ALH is an intermediary device, which acts as a hub and provides an
abstracted support for numerous sound interfaces (e.g. SoundWire).
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The SPI peripheral on SiFive parts uses FIFOs for Rx and Tx (FIFO size
undocumented, but empirically found to be 8 bytes on FE310, likely
identical on FU540 / FU740). Make use of these FIFOs in order to
continuiously feed Tx data as available.
Verified to transmit 1 MHz SPI @ 200 MHz coreclk / tlclk on FE310
continuously without downtime between frames.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
spi_context uses uint8_t buffers, and HW rxdata / txdata registers only
contain 8 bits of data (along with b31 full / empty flag), so uint8_t is
appropriate.
Suggested-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
mux_enabled check in the gsm_configure is unnecessary since it
is init and scheduled by gsm_ppp_start which means that the
mux must be disabled. The IS_ENABLED(CONFIG_GSM_MUX) check
should be good enough to determine whether or not the
mux_enable function should be ran.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
After the introduction of start/stop & rssi query work, these
additional functions can be invoked from different threads.
Things can quickly become hard to analyze when an interrupt
fires during one of these functions and upon return the
scheduler schedules another thread and run another function.
This PR introduces a simple mutex lock that guarantees thread
safety. Similar implementation can be found in hl7800 driver,
which has lots of public APIs that can be invoked from different
threads.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Update gsm_ppp.c
Move the rssi query part out from the rssi_handler work item as
an individual function, so that it can be used directly without
referencing the work.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Fix#46112 introduced a regression regarding rx fifo length.
This fixes it so that the last byte is not placed in
wrong buffer index.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
To support both 8-bit and 32-bit Control/Status register variants, register
offsets need to be calculated from device tree.
Updated register data in device tree to the 32-bit CSR variant.
Renamed defines to be similar to other LiteX drivers.
Changed frequencies in clock-outputs nodes, so i2s/litex sample works.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Correct width when accessing LITEETH_RX_LENGTH register.
Also update register data in device tree to the 32-bit CSR variant.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
LiteX HAL should be used when accessing Control/Status registers to provide
compatibility between different data widths of CSRs.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make driver take register info from device tree so it can work with both
8-bit and 32-bit CSRs.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
anomaly_122_init() and anomaly_122_uninit() procedures implement
proper activate and deactivate procedures which are required for
achieve low power consumption.
The real workaround for the anomaly is buried inside hal function
nrf_qspi_disable() is called indirectly by the anomaly_122_uninit().
Therefore anomaly_122_init/uninit should be called for any
nrf QSPI device.
This patch renames functions and make call to them mandatory.
This fixes increased power consumtion issue on nRF53 device when
qspi was used.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This add UART_NS16550_VARIANT_16550 configuration inside the choice
of UART_NS16550_VARIANT_NS16750 and UART_NS16550_VARIANT_NS16950.
The configuration is enabled by default to make NS16550 device to get
correct FIFO size configuration (16 bytes).
fixes#45783
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
The current sam0 adc driver not implement correctly the adc_reference
enum values. This try homonize adc input referece by tracking VDDANA
at ADC_REF_VDD_1. The ADC_REF_VDD_1_2 were fixed with correct INTVCCx
channel selection.
Fixes#45443
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
