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drivers: spi: spi_litespi: Update driver registers

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Make driver take register info from device tree so it can work with both
8-bit and 32-bit CSRs.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
This commit is contained in:
Michal Sieron 2022-05-23 15:17:45 +02:00 • committed by Marti Bolivar
commit 9f6c531da0
3 changed files with 27 additions and 19 deletions
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16
drivers/spi/spi_litespi.c
View file

@ -68,14 +68,14 @@ static int spi_config(const struct spi_config *config, uint16_t *control)
/* Set Loopback */
if (config->operation & SPI_MODE_LOOP) {
litex_write8(SPI_ENABLE, SPI_LOOPBACK_REG);
litex_write8(SPI_ENABLE, SPI_LOOPBACK_ADDR);
}
/* Set word size */
*control = (uint16_t) (SPI_WORD_SIZE_GET(config->operation)
<< POSITION_WORD_SIZE);
/* Write configurations */
litex_write8(cs, SPI_CS_REG);
litex_write16(*control, SPI_CONTROL_REG);
litex_write8(cs, SPI_CS_ADDR);
litex_write16(*control, SPI_CONTROL_ADDR);
return 0;
}
@ -84,18 +84,18 @@ static void spi_litespi_send(const struct device *dev, uint8_t frame,
uint16_t control)
{
/* Write frame to register */
litex_write8(frame, SPI_MOSI_DATA_REG);
litex_write8(frame, SPI_MOSI_DATA_ADDR);
/* Start the transfer */
litex_write16(control | SPI_ENABLE, SPI_CONTROL_REG);
litex_write16(control | SPI_ENABLE, SPI_CONTROL_ADDR);
/* Wait until the transfer ends */
while (!(litex_read8(SPI_STATUS_REG)))
while (!(litex_read8(SPI_STATUS_ADDR)))
;
}
static uint8_t spi_litespi_recv(void)
{
/* Return data inside MISO register */
return litex_read8(SPI_MISO_DATA_REG);
return litex_read8(SPI_MISO_DATA_ADDR);
}
static void spi_litespi_xfer(const struct device *dev,
@ -158,7 +158,7 @@ static int spi_litespi_transceive_async(const struct device *dev,
static int spi_litespi_release(const struct device *dev,
const struct spi_config *config)
{
if (!(litex_read8(SPI_STATUS_REG))) {
if (!(litex_read8(SPI_STATUS_ADDR))) {
return -EBUSY;
}
return 0;

14
drivers/spi/spi_litespi.h
View file

@ -13,13 +13,13 @@
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#define SPI_BASE_ADDR DT_INST_REG_ADDR(0)
#define SPI_CONTROL_REG SPI_BASE_ADDR
#define SPI_STATUS_REG (SPI_BASE_ADDR + 0x08)
#define SPI_MOSI_DATA_REG (SPI_BASE_ADDR + 0x0c)
#define SPI_MISO_DATA_REG (SPI_BASE_ADDR + 0x10)
#define SPI_CS_REG (SPI_BASE_ADDR + 0x14)
#define SPI_LOOPBACK_REG (SPI_BASE_ADDR + 0x18)
#define SPI_BASE_ADDR DT_INST_REG_ADDR(0)
#define SPI_CONTROL_ADDR DT_INST_REG_ADDR_BY_NAME(0, control)
#define SPI_STATUS_ADDR DT_INST_REG_ADDR_BY_NAME(0, status)
#define SPI_MOSI_DATA_ADDR DT_INST_REG_ADDR_BY_NAME(0, mosi)
#define SPI_MISO_DATA_ADDR DT_INST_REG_ADDR_BY_NAME(0, miso)
#define SPI_CS_ADDR DT_INST_REG_ADDR_BY_NAME(0, cs)
#define SPI_LOOPBACK_ADDR DT_INST_REG_ADDR_BY_NAME(0, loopback)
#define POSITION_WORD_SIZE 8
#define SPI_MAX_CS_SIZE 0x100