This kconfig option enables runtime configuration of UART
controllers. This allows application to call uart_configure()
to configure the UART controllers and calling uart_config_get()
to retrieve configuration. If this is disabled, UART controllers
rely on UART driver's initialization function to properly
configure the controller. The main use of this option is mainly
code size reduction.
Fixes#16231
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Instead of having a hard-coded maximum instance count, introduce a
Kconfig variable for it. The inclusion of the per-instance header
files is solved by having them chain-include each other with a
pre-processor condition that checks if the current header file is the
last one or not.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The reg-shift support was quite broken in that the code only looked
for this property on instance 0. Now we support the property on any
node which might declare it.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Take advantage of DT_INST_FOREACH_STATUS_OKAY() to look for DLF and
PCP properties on any matching nodes with "okay" status.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The existing method of testing for any of the first four DT instances
having the pcie property feels a bit clumsy and will get more so when
support for more than four UARTs is added. A much more cleaner way to
do this (and more correct probably as well) is to list any PCIe-based
UART nodes under a pcie bus in the Device Tree hierarchy.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
currently pcie_get_mbar only returns the physical address.
This changes the function to return the size of the mbar and
the flags (IO Bar vs MEM BAR).
Signed-off-by: Maximilian Bachmann <m.bachmann@acontis.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This gets a little complicated as the driver could be
using PCI-E MMIO, MMIO specified by DTS, or I/O ports.
This driver doesn't use struct uart_device_config any
more.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
PCI devices on 64 bit systems can be mapped anywhere, not just in the
lower 4G of memory. Remove pointer size assumptions.
Also this removes the use of a struct uart_device_config to store the
(runtime) BAR address. That struct has other stuff in it, and the
only thing we need is the single MMIO address. It's also REALLY
confusing to have two "devconf" fields in the device storing values of
the same struct type, some fields of which are used from one of them
but some from the other!
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When PCIe is enabled for UART, the port address is probed during
initialization and is written back into the device config struct.
However, the device config struct is supposed to be const and
read only. This results in page faults when MMU is enabled as
the struct cannot be written into. So fix this by storing port
address in device data struct if a particular UART instance is
of PCIE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The init function returns successful even if the first
configuration function call fails. This may leave
a non-usable UART to be discoverable with
device_get_binding() which will definitely result
in lots of head scratching. So change the init function
to return properly.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The existing uart driver ns16550 did not have ISR locking that
effected IO APIC working in fixed delivery mode in SMP system
x86_64. This commit adds ISR locking mechanism using spinlock
for the interrupt related services.
The CONFIG_IPM_CONSOLE_STACK_SIZE is increased to lift
limitation of stack size experienced in IPM driver test with
this spinlock impelentation.
Fixes#23026
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
This reverts commit 8739517107.
Pull Request #23437 was merged by mistake with an invalid manifest.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
Update device data with the activated configuration, so that it
will be remembered for follow up configuration get requests.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
Change to code to use the automatically generated DT_INST_*
defines and remove the now unneeded configs and fixups.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
The sole purpose of init options has been to enable hardware flow
control on NS16750 when asked. Use the proper DTS tags for this.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
There is only one possible command, so just use if instead of switch
to avoid several MISRA-C violations and also avoid set dev_data wrongly
unused when UART_NS16550_DLF_ENABLED is defined.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The NS16550 UART driver is currently hard-coded as 8-n-1
with no flow control. The baud rate is set by what is in DTS.
This commit moves away from hard-coded and strictly DTS to
configurable using the UART configure API. Requires commit #bcb807.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
The UART configure API was added to uart.h and this commit
implements the initial framework for the configure API for
the ns16550 uart. This includes the configure() and config_get()
functions and uart device configuration structures of the uart
configure API for the ns16550.
Note this commit does not resolve the pre-existing hard-coded
8-n-1 implementation.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
Several macros were documented as deprecated but lacked the
infrastructure to produce deprecation warnings. Add the deprecation
marker, and fix the in-tree references to the deprecated spellings.
Note that one non-deprecated macro should have been deprecated, and
is, referring to a newly added line control bit.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
In some hardware,e.g. ARC HS Development kit,the
peripheral space of ns16550 only allowes WORD
access, byte acess will raise bus error.
This commit adds support for this case
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
move uart.h to drivers/uart.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move sys_io.h to sys/sys_io.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Per guidelines, all statements should have braces around them. We do not
have a CI check for this, so a few went in unnoticed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The per-UART configuration is boilerplate that is becoming a maintenance
nightmare as it grows. A template file is created, and instances are
created as needed by cmake at build time.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A new function pcie_irq_enable() is added to be used in lieu of
irq_enable() when the target device is PCI(e)-attached. The function
attempts to use MSI, when configured in the kernel and supported by
the endpoint; failing that, it will verify that IRQ requested is in
fact routed to the device by the boot firmware before enabling it.
The NS16550 UART driver is updated to use pcie_irq_enable().
The PCI(e) shell is extended to dump information about wired IRQs.
The up_squared devicetree is fixed (reverted?) to IRQ5 for UART1.
The galileo enables MSI by default.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This value always comes from DTS. No Kconfig symbol named
NS16550_REG_SHIFT ever existed.
Might've been missed in commit 603f068690 ("uart/ns16550: Use DT_ prefix
for remaining device configs").
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The UARTs on the Apollo Lake SoCs have PLLs that feed the baud rate
generators. This patch allows a user to specify custom M/N values for
those PLLs when custom/high-speed baud rates are required.
I'm not entirely satisfied with the way the PCP values are configured,
because it requires tweaking data in both Kconfig and DeviceTree. For
the time being I've merely taken my cue from another similar feature
(the DLF register support) and have punted on figuring out the "right
way" to expose UART configuration to the application.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Previous rename from CONFIG_* to DT_* left a few remaining
CONFIG_*. So rename them manually now.
Fix#13753
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is an application facing define, specific to this
driver, for the public uart_drv_cmd() API. Put it with
public headers.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
