Commit graph

2980 commits

Author SHA1 Message Date
Carlo Caione
983d4606ff ipc_service: Add new RPMsg with static VRINGs backend
Introduce a new RPMsg with static VRINGs backend. This new backend makes
easy to generate and use IPC instances backed by OpenAMP using the DT.

Each instance is defined in the DT as (for example):

  ipc: ipc {
          compatible = "zephyr,ipc-openamp-static-vrings";
          shm = <&sram_ipc0>;
          mboxes = <&mbox 0>, <&mbox 1>;
          mbox-names = "tx", "rx";
          role = "primary";
          status = "okay";
  };

It is then possible to register an send data through endpoints using the
IPC service APIs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-11-22 23:03:23 -05:00
Peter Johanson
d99de305ce dts: bindings: Add generic Xiao interconnect
* With existence of Adafruit Qt Py boards, and upcoming wireless
  Xiao from Seeeduino, define nexus node and peripheral node
  labels for use with shields that accept any Xiao format board.
* Adds `&xiao_d`, `&xiao_spi`, `&xiao_i2c` and `&xiao_serial` generic
  node labels.
* Add new 'seeed-xioa-header.yaml` to document new nexus node.

Signed-off-by: Peter Johanson <peter@peterjohanson.com>
2021-11-22 22:25:20 -05:00
Gerard Marull-Paretas
285f55899b drivers: serial: gd32: use pinctrl
Use the pinctrl API to configure peripheral pins.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
1f74c01daa dts: arm: gigadevice: gd32f403: add afio and pinctrl
Add afio, pinctrl and gpioa...g entries for the GD32F403 series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
f8017dc5ad drivers: pinctrl: gd32: initial support for AFIO based SoCs
Add a pin control driver for GD32 SoCs using the AFIO model.

Thanks to Gerson Fernando Budke for testing and implementation
suggestions.

Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
63321e7f73 dts: arm: gd32f4xx: add pinctrl and gpio nodes
Add definitions for the pinctrl and gpio nodes.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
543a3843ff drivers: pinctrl: gd32: initial support for AF based SoCs
Add a pin control driver for GD32 SoCs using the AF model.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Wealian Liao
5a9bc389f0 driver: gpio: nct38xx: Add NCT38XX gpio driver support
NCT38XX series, which are i2c-based chips, support a different number
of GPIO functionality. For NCT3807, it has 2 GPIO ports on the same i2c
device address. For NCT3808, it has 2 GPIO ports on different i2c
device addresses. This commit adds NCT38XX GPIO driver support &
provides the interrupt handler for the share alert pin.

The following is NCT3807 devicetree node example:
```
&i2c0_0 {
	nct3807_0: nct3807@70 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nuvoton,nct38xx-gpio";
		reg = <0x70>;
		label = "NCT3807_0";

		gpio@0 {
			compatible = "nuvoton,nct38xx-gpio-port";
			reg = <0x0>;
			label = "NCT3807_0_GPIO0";
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <8>;
			pin_mask = <0xff>;
			pinmux_mask = <0xf7>;
		};

		gpio@1 {
			compatible = "nuvoton,nct38xx-gpio-port";
			reg = <0x1>;
			label = "NCT3807_0_GPIO1";
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <8>;
			pin_mask = <0xff>;
		};
	};
};
```

Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-11-20 08:00:38 -05:00
Ruibin Chang
3ab081efe9 ITE drivers/pwm: cleanup it8xxx2 pwm driver
1.Putting the PWM_CHANNEL_X, PWM_PRESCALER_CX information
  in the description.
2.Use the common definition EC_FREQ.
3.Use the common macro IT8XXX2_DT_ALT_ITEMS_LIST.
4.Stop using DRV_CONFIG, DRV_REG macro.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-11-19 10:24:11 -06:00
Tomasz Bursztyka
4bd5935302 dts/bindings: Add a dedicated property for duplex mode on SPI device
Users will have to include dt-bindings/spi/spi.h in order to use the
relevant flags fol this property. For instance:

    ...
    duplex = <SPI_HALF_DUPLEX>;
    ....

By default all SPI device are configured to be full duplex so the
property is optional. This property makes sense only for devices that
can be configured on either modes. Which, in such case, it will need to
use DT_INST_PROP(<instance number>, duplex) macro call to retrieve the
property value. Others can fully ignore it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-19 11:50:38 +01:00
Tomasz Bursztyka
20b8d74d42 dts/bindings: Update HTS221 bindings to enable both i2c and SPI bus
HTS221 is now supported on both buses so let's make DTS aware of it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-19 11:50:38 +01:00
Gerard Marull-Paretas
1832d68e01 tests: lib: devicetree: add tests for DT_INST_ENUM_IDX(_OR)
Add tests for the instance based enum macros DT_INST_ENUM_IDX and
DT_INST_ENUM_IDX_OR.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-18 19:12:07 -05:00
Gerard Marull-Paretas
13b011afb9 dts: arm: gigadevice: add support for gd32f450ik
Add support for the IK variant (256K SRAM, 3072K ROM).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
c34f41b22d dts: arm: gigadevice: add initial support for gd32f4xx
Add initial support for GD32F4XX (405, 407 and 450).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
809c35d430 dts: arm: gigadevice: organize dts files in folders
Create a folder for each of the series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
David Leach
a09ba37334 MXRT600: Fix secure/non-secure definition for FLEXSPI
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.

Changes include:

- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
2021-11-18 14:29:53 +01:00
Tim Lin
e29a15c0e3 ITE: drivers/serial: add the UART driver for the PM callback function
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.

note: pm_action_cb(old name: pm_control_fn)

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-11-16 21:23:42 -05:00
Alexandre Bourdiol
37ffd01f8c dts: arm: stm32: TIM6 and TIM7 doesn't support PWM capability
TIM6 and TIM7 doesn't have comparator, nor pin output.
Thus they can't support PWM.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-11-16 09:55:30 -06:00
Alexandre Bourdiol
7f3423ae48 dts: arm: st: stm32: move "st,prescaler" to timers instead of pwm
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-11-16 09:55:30 -06:00
Alexandre Bourdiol
37175e8643 dts: bindings: stm32: move "st,prescaler" to timers instead of pwm
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
Also prescaler is common to all PWM channels of the same timer.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
For compatibility reason temporarily keep pwm binding to avoid
breaking boards out of tree.
Block st,prescaler property in lptim binding
as lptim doesn't use this property for now.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-11-16 09:55:30 -06:00
Lukas Gehreke
0544f5dbc3 drivers: gpio: Added mcp230xx GPIO driver.
Added driver for the mcp230xx series I2C-based GPIO chips.

Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
2021-11-16 10:13:14 -05:00
Dino Li
6d8f1bf6d9 soc: it8xxx2: add support for eSPI driver
This supports eSPI slave, virtual wire, and peripheral functions.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-11-12 14:51:10 +01:00
Felipe Neves
b50cb2a537 drivers: counter: esp32: add support for esp32c3
to the unified esp32 counter driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-11 19:14:15 -05:00
Martí Bolívar
d2ba94bbea dts: nordic,nrf-radio: add fem property
This will be used to take a phandle to a FEM device, either a generic
two pin device or an nRF21540. Keep the nRF21540 binding example up to
date.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-11-11 21:52:24 +01:00
Martí Bolívar
a930bebb42 dts: bindings: improve nordic,nrf21540-fem docs
The way the nRF21540 device is configured makes sense once you
understand it, but it's quite unusual: a single peripheral is
configured with two separate devicetree nodes linked by a phandle.

Since this risks entering "exploding head" territory for beginners, it
deserves a thorough example. Add one to the binding's description.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-11-11 21:52:24 +01:00
Martí Bolívar
9bbaccc8ed dts: bindings: add generic-fem-two-ctrl-pins
This is a helper binding for radio front-end modules that have a
two-pin control interface, where one pin is used to turn on an power
amplifier (PA) for TX, and another is used to turn on a low-noise
amplifier (LNA) for RX.

Such hardware is already supported by the Bluetooth subsystem, but via
PA/LNA Kconfig settings. Since this is hardware configuration, it is
better to move this to devicetree instead.

Add a binding that makes it possible to define nodes which contain the
same information, along with a bit of extra information related to the
gain in dB of each amplifier not currently available from Kconfig.
This is similar to the existing binding for the nordic,nrf21540-fem
compatible.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Andrzej Kuros <andrzej.kuros@nordicsemi.no>
2021-11-11 21:52:24 +01:00
Martí Bolívar
3eb2377c58 dts: sitronix,st7789v: fix binding whitespace
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-11-10 17:28:17 -05:00
Carlo Caione
74b701065d bindings: nrf-ipc: Enable DT helpers
Make the MBOX NRF IPC instances referenceable using the MBOX DT helpers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-11-10 10:28:14 -06:00
Jonathan Rico
4f2762d7da dts: Add external coexistence pointer to nrf-radio
This is to support upcoming external radio coexistence implementations,
see binding documentation for more info.

Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
2021-11-10 16:11:41 +01:00
Neil Armstrong
2825481747 devicetree: add tests for devicetree ranges API macros
Test cases for new APIs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-10 08:23:00 -05:00
Nick Ward
fa94be591d drivers: spi_nrfx_spim: workaround for nRF52832 errata anomaly 58
See:
https://infocenter.nordicsemi.com/index.jsp?topic=%2Fstruct_nrf52%2Fstruct%2Fnrf52832_errata.html
https://infocenter.nordicsemi.com/pdf/nRF52832_Rev_3_Errata_v1.0.pdf

Code derived from the example PAN 58 workaround code.

Adds a new nRF SPIM Devicetree binding property called
anomaly-58-workaround that allows the workaround to be enabled
if required per SPIM instance.

Signed-off-by: Nick Ward <nick.ward@setec.com.au>
2021-11-09 20:04:45 -05:00
Francois Ramu
5c1fa04b2c dts: arm: stm32U5 add the ADC1 and ADC4 nodes
This PR enables the ADC peripheral for the stm32U5 soc
series from STMicroelectronics.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-11-09 15:59:23 -06:00
Felipe Neves
857a188c76 drivers: watchdog: esp32: enabled esp32c3
support for the unified esp32 wdt driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-08 10:56:28 -05:00
Andrei-Edward Popa
5413661a81 boards: xtensa: add ledc support to the esp32 board
add ledc to board dtsi file,
change compatible and device define in pwm driver,
add yaml for board ledc support,
fix missing include for board in gpio include

Signed-off-by: Andrei-Edward Popa <andrei_edward.popa@upb.ro>
2021-11-07 05:36:42 -05:00
Sylvio Alves
ab91612a6d driver: esp32: I2C code refactoring
Use i2c_hal functions to enable support for
multiple SoCs.

Use DT compat to enable I2C from device
tree configuration

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-05 14:07:09 -04:00
Sylvio Alves
27e44acda1 clock: esp32: unify clock control for all espressif socs
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-04 15:21:26 -04:00
Francois Ramu
261d14b58b dts/arm: stm32u5: add usb OTG full-speed node
Add the USB On-The-Go Supplement, Revision 2.0 in the DTS
of the stm32u575 and stm32u585 devices
(not for the stm32U5 serie).

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-11-04 10:25:17 -05:00
Francois Ramu
5b070d28f3 dts/arm: stm32u5: add System window watchdog node
Add the WWDG node for stm32u5 socs.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-11-04 10:18:53 -05:00
Tomasz Bursztyka
19836913d8 dts/x86: Enable PTM root device
Port 0 exposes such capability.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-04 11:06:02 -04:00
Tomasz Bursztyka
e854950219 dts/pcie: Add PTM root device specification
It only requires a proper reg property to be filled-in.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-11-04 11:06:02 -04:00
Sylvio Alves
d5aa5c2a77 drivers: esp32: uart: use hal functions
In order to have Espressif SoCs working with
the same uart drivers, all low level functions
are now replaced to hal_espressif HAL calls.

This also changes pinmux, gpio and uart
init order to meet its dependencies.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-03 16:47:32 -04:00
Erwan Gouriou
1a73c39dfc dts/bindings: clock: cpu2-prescaler is optional on stm32wl
STM32WL could be either single core (stm32wlex) or
dual core (stm32wl5/4x).
Make CPU2 prescaler an optional property (while it will
be required if inherited from st,stm32wb-rcc.yaml.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-03 16:19:06 -04:00
Erwan Gouriou
bbe47ee529 dts/bindings/clocks: stm32: Set RCC properties as mandatory
Now that Kconfig option for STM32 clocks configuration has been
removed, set rcc properties as required.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-03 16:19:06 -04:00
Daniel DeGrasse
309dfe7cfe boards: mimxrt1160_evk: Fix DTS inconsistencies with reference manual
Fix register addresses in rt11xx SOC dts. Flexcan1 was defined with an
incorrect register address, and watchdog 3 was incorrectly labelled as
watchdog 1. Watchdog 2 should not be enabled, as it is only accessible
from code running in the trustzone context.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-11-03 16:18:25 -04:00
Daniel DeGrasse
c0cee4fb5c boards: Add support for NXP RT1160 EVK
Add baseline support for mimxrt1160_evk Cortex M4 and M7 cores
UART shell, synchronization, and hello world have all been verified to
build and run correctly.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-11-03 16:18:25 -04:00
Henrik Brix Andersen
6b4a2d3e47 dts: can: nxp: flexcan: specify sample point instead of time quanta
Convert all in-tree NXP FlexCAN instances from hardcoding the CAN bus
timing in time quanta to specifying a desired sample point of 87.5% as
recommended by CAN in Automation (CiA).

This allows for the CAN driver to calculate the optimal time quanta
based on the CAN clock and the requested CAN bitrate.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-11-02 22:28:00 -04:00
Wouter Cappelle
8cdc822954 dts: arm: Add devicetree files for STM32L010xB series microcontrollers
This PR adds the devicetree file for supporting the STM32L010xB mcu.

Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
2021-11-02 22:21:45 -04:00
Erwan Gouriou
5fb5b7fff8 dts: stm32: Add interrupts to "st,stm32-sdmmc" nodes
Add interrupts property to "st,stm32-sdmmc" nodes to enable
use of IT driven mode.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-11-02 22:20:36 -04:00
Tom Burdick
73f343c51e board: Adds RDDRONE-FMUK66 board support package
Adds required LQ18 part number to the kinetis K66 series

Signed-off-by: Tom Burdick <tom.burdick@electromatic.us>
2021-11-02 13:17:44 -05:00
Krzysztof Chruscinski
9174cd8dbc drivers: watchdog: Add software watchdog based on counter
Added watchdog implementation which is using counter device
to implement watchdog driver API. Watchdog timeout is called from
counter interrupt context. Some counter implementations support
using ZLI interrupt level which can be use here as well. Watchdog
like this can be used along hardware watchdog to cover for its
limitations, i.e. Nordic watchdog resets unconditionally after
62uS after triggering watchdog interrupt. It is not enough time
to dump logging data.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-11-02 13:22:58 +01:00