Converted over all STM32F4 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F4.
Boards that are now using devicetree:
* 96b_carbon
* nucleo f401re
* nucleo f411re
Change-Id: Ibe197ca0a3f5ad78d594485a578d986403cc824a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Cortex-M4 of the STM32F4 family has an FPU. Enable the FPU support
by selecting CPU_HAS_FPU.
Change-Id: Iddae9c547df6e010562649eb0997dc61563c8fc4
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The comment refers to STM32F1 instead of STM32F4.
Change-Id: Ide116b712146f87a6f4d2aaafea8bd181c4d9397
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The current implementation of stm32_gpio_set() uses the GPIO output data
register to change the state of individual GPIOs. The generated
assembler needs at least 3 instructions: load / modify / store.
This opens a small race window, for example if a thread and an
interrupt both try to change the state of the same GPIO bank.
Use the GPIO bit set/reset register to perform the atomic change without
locking.
This also has the benefit of a more optimised implementation, which can
be useful for GPIO-intensive work. Compare the new version:
08000c98 <stm32_gpio_set>:
8000c98: f001 010f and.w r1, r1, #15
8000c9c: 2301 movs r3, #1
8000c9e: b902 cbnz r2, 8000ca2 <stm32_gpio_set+0xa>
8000ca0: 3110 adds r1, #16
8000ca2: 408b lsls r3, r1
8000ca4: 6183 str r3, [r0, #24]
8000ca6: 2000 movs r0, #0
8000ca8: 4770 bx lr
and the old one:
08000c98 <stm32_gpio_set>:
8000c98: 2301 movs r3, #1
8000c9a: f001 010f and.w r1, r1, #15
8000c9e: fa03 f101 lsl.w r1, r3, r1
8000ca2: 6943 ldr r3, [r0, #20]
8000ca4: b10a cbz r2, 8000caa <stm32_gpio_set+0x12>
8000ca6: 4319 orrs r1, r3
8000ca8: e001 b.n 8000cae <stm32_gpio_set+0x16>
8000caa: ea23 0101 bic.w r1, r3, r1
8000cae: 6141 str r1, [r0, #20]
8000cb0: 2000 movs r0, #0
8000cb2: 4770 bx lr
Change-Id: Ie5800d1c345016028d1b9a099f5d74cac35f592a
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The previous file contained erroneous values of the number of IRQs
in these socs.
Change-Id: Ie7d2c19d86e247599f4924b95d9330175140d894
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
Cube HAL implements timeout based on 1ms tick.
This commit allows Cube HAL to get Zephyr system clock.
Change-Id: I9a59edcf6fa8e0ebfd5040348db537dadd9fcdfa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to support the discovery STM32F4 and STM32F429 boards,
it is necessary to make these socs available.
Change-Id: I351d294fb02c4385f291a6e258a3f7d81e85627e
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
A number of SoCs clear out the Mem/Bus/Usage and Hard Fault exceptions
during init. Lets refactor that into a common function so we don't have
to keep duplicating it over and over.
Change-Id: Ida908a9092db37447abcf3c9872f36937982f729
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
It is called before early SoC initialization, so remove the duplicated
code from other boards and just set it by default when using XIP.
This can later be used when adding bootloader support, as an
additional option could be created to move the VTOR offset to a
different address.
Change-Id: Ia1f5d9a066de61858ee287215cefdd58596b6b1c
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
stm32f411re SoC could run at system clock above 84MHz.
This was not taken into account in __setup_flash function which configure
flash latency depending on system clock. This is now corrected.
Assert added to ease error detection.
Change-Id: I49b92256d611ef464171fb1d8812a4c4d3c27ab8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
replace include <nanokernel.h> with <kernel.h> everywhere and also fix
any remaining mentions of nanokernel.
Keep the legacy samples/tests as is.
Change-Id: Iac48447bd191e83f21a719c69dc26233216d08dc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Following pinmux update for PWM support,
update soc to support this new configuration.
Change-Id: I1126e347ab1ab6b2d830993e548de8f32fa2f8f9
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
There was a misalignment between Zephyr UART device numbering and
SoC UART IP. Device "UART_1" was mapped to IP USART_2, which could
be confusing for user.
This commit allows to align "UART_1" to IP USART_1.
Change is propagated to all STM32F103RB/STM32F401RE based boards and
respective pinmux drivers
Change-Id: Ia8099dfeec7b9c0c686c2a58ccb4dbb1a55b6537
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Due to new serial driver implementation based on STM32Cube we can
remove the USARTX_ADDR defines as they aren't ended anymore
Change-Id: Ia9f9b0a2a63280c0221c789a53ff7338bda17dfb
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32Cube based implementation allows single driver file for
all stm32 based SoCs.
By maximizing code reuse, use of STM32Cube eases new SoCs
porting into Zephyr and provides better maintanability and
maturity.
Change-Id: Ief4b723add3dfc8b2a839683559c5a4c5d5eb837
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Make the systick feature optional that can be selected by the SoC.
Change-Id: I4a405640b84daecc17fc1882743d3cafb78ff861
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Enable HAS_CUBE config flag on stm32f4 family soc.h is updated to
include minimum include files from ext/hal/stm23cube
Change-Id: I35a8c33aab777167ee7029edc1b7a4f6d21fccd8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32Cube uses SoC defines made to reflect HW heterogeneity that
should be taken into account by SW.
Aim of this commit is to adapt values used by Zephyr to the same
diversity. This will help create new SoC values only when justified
by a real hardware difference that should be taken into account
by software.
For instance, for SoC stm32f401re following define is used:
*STM32F401xE
Which means:
*Same SW could be used on STM32F401RE and STM32F401CE:
same CONFIG_SOC could be used
*Different SW should be used on STMF401RE and STM32F401RC:
different CONFIG_SOC should be used
This change focuses on stm32f4xx series.
Change-Id: I56ff4d1815d09747cf722385532eb2dcbdf37b44
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move common config options one level up to try to simplify the per-board
defconfig
Change-Id: I3d80fa494050634d0f877af2015b01b85df20d1d
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for the STM32F401 chip on the board
Change-Id: I96c0799f3658ecea096fa5971bce9faf21919ee1
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32F401 allows for upto 16 alternate functions on each pin.
Change-Id: Ib1c14fd31abaa2b05a5ab0f7bd1b4a4748f10f84
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Implements MCU-specific GPIO input interrupt integration. Added
definition of System configuration controller as well as its needed by
the GPIO code.
The SYSCFG controller is used for system-specific configuration such as:
- remap the type of memory accessible at address 0x00000000
- manage the external interrupt line connection to GPIOs
- configure the I/O compensation cell
Change-Id: Id2ebfbd1b21e77be76406d1cd6cd5d4989e9e2fa
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Based on the STM32F10x driver. Removing old code as we need to use the
bus number when dealing with 4 possible peripherals.
Change-Id: Id0263aa008e9b039ff9a00339e5622e289ffdf99
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds support for the STMicroelectronics STM32F4x family in the
STM32 MCU line. Configuration is included for the STM32F401RE MCU.
Acknowledgements to Pawel Wodnicki's earlier submission from February that
was used as a starting point for this port. In the end, we rewrote all of it.
Change-Id: I9797c282ac3c0cc66a63b9d34821de95df537ef6
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
