Now that we can specify what toolchain is intended for each
SOC, enable some more SOCs to be built.
A full sanitycheck run will require the installation of both
RF-2016.4 and RG-2016.4 releases.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
XTENSA_TOOLS_PATH and XTENSA_BUILDS_PATH have been retired.
XTENSA_SDK is now the base directory for the Xtensa SDK. The build
systems will search for toolchains in there, using
CONFIG_TOOLCHAIN_VARIANT to locate the right one. It defaults to
/opt/xtensa.
XTENSA_BUILD_PATHS is now a list of additional directories to search
for Xtensa CPU builds. By default the build system will already search
the builds included in the SDK; this is intended for vendor-supplied
CPU build definitions.
Some whitespace changes made for readability and comments added.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This greatly increases the speed in which test cases are evaluated
on the Xtensa simulator.
The cycle limit parameter was removed, we don't currently need it
since sanitycheck handles killing test cases if they time out.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
classname seems to be expected by some parsers, so use it in the report,
the name now has the same value, we can add some more information once
we have meaningful metadata for the testcases with more details.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This new options makes it possible to only run a subset of the tests
which will allow us to run sanitycheck on multiple hosts and merge the
results into one report. This way we do not need to worry about
selecting specific architectures to be run on a certain host.
The option accepts a string value: x/y where x is the subset and y is
the total, so if we specify --subset 1/5, we will only run the first
fifth of the total tests, --subset 5/5 would only select the last fifth.
To get consistent results, the testcase instance list is now ordered,
to avoid duplications and have full coverage.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add necessary board files, pinmux and device tree in order to have a
usable debug console.
Origin: Original
Change-Id: I280320700352fd36a544c03f4e57d2eeec2449e5
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Adds a new debug support script using pyOCD and configures most NXP
boards so they can use it. frdm_kw41z is the one exception because pyOCD
doesn't yet support kw41z. Tested with pyOCD v0.8.0 and the latest
DAPLink firmware for each board.
Introduces two new environment variables, PYOCD_FLASHTOOL and
PYOCD_GDBSERVER, that allow you to set custom paths to the pyOCD tools.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a new debug support script using Segger JLink and configures all
NXP boards so they can use it. Tested with Segger JLink GDB server
V6.14b and OpenSDA v2.1 firmware.
Change-Id: Ia1b297d9c93d21db61379e22f27ae54cda3ad461
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
C library is not actually used by the xtensa port, we only need the
'exit' function. Implement 'exit' in crt1-* and drop remaining
references to the C library.
Change-Id: I8a562363956b4755a6b5baee7acf3726485e5ce3
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Building zephyr for xtensa with gcc requires additional include paths and
additional library (libhal).
Add xtensa sysroot and include paths to CFLAGS when building for xtensa.
The root Makefile then does the right thing adding these parameters to
KBUILD_CFLAGS and KBUILD_ASFLAGS.
Add xtensa libhal to the TOOLCHAIN_LIBS_xtensa. Modify TOOLICHAIN_LIBS to
include arch-specific libraries.
Seems that it would be nice to have TOOLCHAIN_CFLAGS_$(ARCH) with the
same behavior as TOOLCHAIN_LIBS_$(ARCH). It also seems that the SYSROOT
definition doesn't have to be restricted to MAKEFILE_TOOLCHAIN_DO_PASS2.
Change-Id: Ia6703ca067b964ac2f8be8fe8513ca28f101a6a3
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This core configuration was removed from the tree since it cannot
implement irq_offload().
Remove an orphaned block in xtesna.ini.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add configuration, dts and documentation for the Nucleo L432KC board
based on the STM32L432KC SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Make sure we get full name in the commit message and not the username or
some incomplete data that we need to decipher. We still need to verify
the commiter name that is not part of the commit message body, but this
is out of scope of gitlint.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit provides support for disco_l475_iot1 board
Pinmux driver is provided with initial support definitions
Change-Id: I17b637a8ba0b033014969eca8fffe76319c47c52
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to allow the use of such board, a very preliminar port was
developed. It consists of board files, as well as pinmux, uart, gpio,
spi drivers and device tree files.
Change-Id: I5753064e39e0b023cf4481744c176de26d8dbebb
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CC3220SF_LAUNCHXL effectively replaces the CC3200_LAUNCHXL,
with support for the CC3220SF SoC, which is an update for
the CC3200 SoC.
This is supported by the Texas Instruments CC3220 SDK.
Jira: ZEP-1958
Change-Id: I2484d3ee87b7f909c783597d95128f2b45db36f2
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Add initial .shippable.yml for CI integration on github and related
scripts.
Change-Id: I095d125e780bba980e635e218205c8741e753a8e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Currently running "make V=1 flash/debug" does not result in the caller
discovering what commands are run to perform the action because make
calls into an opaque script (which then makes complex invokations of
both openocd and gdb). Make the script more transparent by conditionally
enabling enabling tracing within the script.
We also remove the "Done flashing" message. It is pointless because
openocd has already *told* us it has done flashing ["wrote 16384 bytes
from file .../zephyr.elf in 0.802135s (19.947 KiB/s)"]. It is also
potentially misleading since it tells us we are "Done flashing" even
when we failed to flash anything which risks misleading someone
unfamiliar with openocd.
Change-Id: Icaea28c4b00ac10965726dd4502162b7de080953
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Generate a test report using junit/xunit format with all details and
logs that can be published on the web to show results from a sanitycheck
run.
Output is stored in scripts/sanity_chk/ alongside the CSV file.
Change-Id: I5ea6f409c1f86f408eeae870b90a953e71046da9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Install gitlint using pip:
# pip install gitlint
# gitlint install-hook
This will install the pre-commit hook.
Policies are define in .gitlint. Custom rules are available under
scripts/gitlint.
This script will also run in CI, so avoid CI errors by using the hook
above.
Change-Id: I62750a1fd9369341db29c413a6c4a1677bb0db8a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
To speed up builds, this change allows building the needed host tools
that are built for every application and stores them un
${ZEPHYR_BASE}/bin.
Run 'make host-tools' and then define PREBUILT_HOST_TOOLS to reuse the
host tools across multiple builds.
$ make host-tools
HOSTCC scripts/basic/fixdep
HOSTCC scripts/gen_idt/version.o
HOSTCC scripts/gen_idt/gen_idt.o
HOSTLD scripts/gen_idt/gen_idt
HOSTCC scripts/gen_offset_header/gen_offset_header.o
HOSTLD scripts/gen_offset_header/gen_offset_header
HOSTCC scripts/kconfig/conf.o
SHIPPED scripts/kconfig/zconf.tab.c
SHIPPED scripts/kconfig/zconf.lex.c
SHIPPED scripts/kconfig/zconf.hash.c
HOSTCC scripts/kconfig/zconf.tab.o
HOSTLD scripts/kconfig/conf
$ export PREBUILT_HOST_TOOLS=${ZEPHYR_BASE}/bin
$ make -C samples/hello_world
Now you will notice a speedup when building the application!
Change-Id: Ie0aeee7f9a60b1fd49e7e32d78601f03473d73b8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Only in rare cases should we allow C99 types, so lets warn about it to
catch issues.
Change-Id: I2bacdd4ba98f88482e0b7acc0567ff1139e749bf
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Hex mumeric values directly in the expression were cast correctly
via the t_HEX rule, but ValueErrors would occur if a hex value was
looked up due to the expansion of some environment symbol.
Change-Id: Ia98dfea91eff4ed95778922d38d2967284f4e31b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Yes, revert the revert, was a little too quick to apply this. The fix
is to cleanup the dtsi file in question.
This reverts commit 6702686976.
Change-Id: I933fad9d96ec6375eda33f0b012349f1c39e261f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
* CONFIG_SOC is now properly set and we do not need a separate
XTENSA_CORE build variable
* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed
* There is no default SOC selection, it is now done explicitly in
the board's defconfig
* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
uppercase> to conform to established style.
Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This reverts commit 1c06065941.
Breaks cc3200_launchxl really bad:
CC drivers/serial/uart_cc32xx.o
/projects/zephyr4/drivers/serial/uart_cc32xx.c:39:18: error: ‘TI_CC32XX_UART_4000C000_BASE_ADDRESS’ undeclared here (not in a function)
.base = (void *)TI_CC32XX_UART_4000C000_BASE_ADDRESS,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/projects/zephyr4/drivers/serial/uart_cc32xx.c: In function ‘uart_cc32xx_init’:
/projects/zephyr4/drivers/serial/uart_cc32xx.c:65:5: error: ‘TI_CC32XX_UART_4000C000_BAUD_RATE’ undeclared (first use in this function)
TI_CC32XX_UART_4000C000_BAUD_RATE,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Change-Id: If46c239bc8d6b4296494f638e900f6044a92ce26
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch fixes an issue with mixed case node names. Node names
containing upper case letters were causing key match errors during
post processing. This patch maintains the case of the node names.
Change-Id: I153a186fa09dcf958c9de55b578dbc63e615a076
Signed-off-by: Andy Gross <andy.gross@linaro.org>
A patch moved the specification of debug flags to a
KBUILD_CFLAGS_OPTIMIZE, but this Makefile wasn't updated.
Change-Id: Ic0d23f95609798473298cda4c044981edabb3ed5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is intended as a temporary fix for ZEP-1882.
Investigation for this bug has shown that the current SDK 0.9 compiler
for ARC generates incorrect code under -Os optimization level.
Kuo-Lang Tseng found out that SDK 0.8.2 does not have this issue, and
that lowering optimization level to -O2 fixes the issue with SDK 0.9.
Juro Bystricky is working on an updated SDK with ARC GCC 6.3.0, but
there are still problems with it, so he also suggested to use -O2 in
the meantime.
Instead of blindly setting -O2 for all toolchains and architectures,
let Makefile.toolchain.zephyr make the decision for ARC and 0.9 only.
Tested with hello_world, CONFIG_ADC=y and BOARD=arduino_101_sss.
Jira: ZEP-1882
Change-Id: Ifde2e3950c9d93eed8982149805acfda9d13a94f
Signed-off-by: Patrice Buriez <patrice.buriez@intel.com>
