LiteX CSRs can only be accessed on addresses aligned to 4 bytes.
That's why in 32-bit CSRs case there is bit shifting needed.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Removed register sizes from config struct, as they are known.
This allowed to remove driver specific function reading from CSR and use
`litex_write*` functions from LiteX HAL.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
With universal LiteX HAL working, there is no need to perform multibyte
reads and writes using bitwise operations.
Just use appropriate `litex_read*` or `litex_write*` function.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds LITEX_CSR_DATA_WIDTH option to Kconfig
Depending on its value appropriate read/write handling is used
for accessing CSR registers.
By using `>=` in preprocessor conditions it is somewhat future-proofed.
Doesn't touch `litex_read` and `litex_write` yet.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Fixed the issue when sometimes "update" is not called for the
last RXRDY signal. First, need to reset the signal and only
after that need to call the "update" function.
Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Currently the driver only setup the ADC to read from the
internal temperature channel on init. However, it is possible
that some other application that uses the ADC can setup the
ADC to read from some other channel and therefore subsequent
stm32_temp_sample_fetch will fail to read the targeted channel.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The ADC should be calibrated on init, there is no requirement
to calibrate ADC again on stm32_temp_init, remove it.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Keys' order - bn, n - might differ from the default due to
Length-First Map Key Ordering rules.
Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
Regenerates the encoder and decoder. Treats integers and floating-point
values as separate entities instead of saying that those are numerical
values. Brings some memory savings.
Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
Makes possible to write an empty CBOR array if there are no SenML CBOR
records that needs to be written. This came up when trying to delete a
portfolio object instance.
Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
With LwM2M v1.1 SenML CBOR is preferred over SenML JSON.
TLV is on by default only with v1.0.
Signed-off-by: Veijo Pesonen <veijo.pesonen@nordicsemi.no>
The peripheral is configured to update the connection
parameters for 5 seconds by default.
There is an abnormal situation with a very low probability.
The central actively disconnects or abnormally disconnects the
Bluetooth connection at the same time.
At this time, the connection disconnection event will be
handled by BT RX.
At this time, sysworkq has sent a parameter update request and
will receive a reply with status = 0x02, because the handle is
invalid at this time.
We can not just cancel work, because work->flag may be
in K_WORK_RUNNING, so work->flag is set to K_WORK_CANCELING
and subsequent conn_cleanup will unable call k_work_rescheduler
successfully.
According submit_to_queue_locked will return ret = -EBUSY.
if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
/* Disallowed */
ret = -EBUSY;
As a result, the connection cannot be cleanup correctly.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
The NAPOT mode isn't computed properly in qemu when the full address
range is covered. Let's hardcode the value that the qemu code checks
explicitly until the appropriate fix is applied to qemu itself.
For reference, here's the qemu patch:
https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00961.html
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
QEMU does its dynamic instruction translation in 4096-byte-sized chunks.
Therefore it doesn't vet PMP access for each instruction prefetch but
for the whole "page" at once. If the end of the ROM area lands in the
middle of such a page with a corresponding PMP entry then any instruction
access within that page will fault even if it is located in the PMP
mapped portion.
To work around this QEMU peculiarity, we simply align the end of the ROM
area to a page boundary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Overall diffstat with the new PMP code in place:
18 files changed, 866 insertions(+), 1372 deletions(-)
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add the appropriate hooks effectively replacing the old implementation
with the new one.
Also the stackguard wasn't properly enforced especially with the
usermode combination. This is now fixed.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The idea here is to compute the PMP register set on demand i.e. upon
scheduling in the affected threads, and only if changes occurred.
A simple sequence number is used to stay in sync with the latest update.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Stackguard uses the PMP to prevents many types of stack overflow by
making any access to the bottom stack area raise a CPU exception. Each
thread has its set of precomputed PMP entries and those are written to
PMP registers at context switch time.
This is the code to set it up. It will be connected later.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This is the core code to manage PMP entries with only the global entries
initialisation for now. It is not yet linked into the build.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Extend sample to show how to use alternative approach of adding
subcommands using new APIs: SHELL_SUBCMD_SET_CREATE, SHELL_SUBCMD_ADD
and SHELL_SUBCMD_COND_ADD.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Added test for new macros in the API for adding subcommands:
SHELL_SUBCMD_SET_CREATE, SHELL_SUBCMD_ADD and SHELL_SUBCMD_COND_ADD.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Added macro SHELL_SUBCMD_SET_CREATE which creates a set of subcommands.
SHELL_SUBCMD_ADD and SHELL_SUBCMD_COND_ADD can be used from any file to
add command to the set. This approach allows to have subcommands added
from multiple files.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Fix the descriptions for the ST STM32 FDCAN devicetree bindings. These
are derivates of the Bosch M_CAN, but they target specific SoC
implementations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the base Bosch M_CAN CAN-FD controller devicetree binding to
match the product name and the upstream Linux devicetree binding.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Fold the simple bosch,m-can devicetree binding into the front-end
devicetree bindings. The bosch,m-can compatible is not used in Zephyr.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Change the default initialization priority for CAN transceiver from 70 to
45 to initialize them before the CAN controllers (with default a
initialization priority of 50).
Fixes: #45219
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
MDB debugger may modify debug_select and debug_mask registers
on start, so we can't rely on debug_select reset value.
Let's set correct value on primary CPU without reading initial
value from debug_select.
Internal ID: P10019563-50516
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Client jump to full registration state if registration update fail.
Update keep already opened DTLS session.
Signed-off-by: Juha Heiskanen <juha.heiskanen@nordicsemi.no>
Enabled DTLS session cache for support session resume.
Fixed LwM2M queue mode for close connection and reconnect automatically.
Re-connect will do Registration update before it send queued data.
Session resume is helping a case when NAT change address and cause less
network traffic.
Signed-off-by: Juha Heiskanen <juha.heiskanen@nordicsemi.no>
When sending 2 or more confirmable message before first one is
writed to socket all messages use same coap pending structure.
Now coap_pending_init() set data pointer which lock allocation
by each call.
Using data pointer for detecting free is more stable than timeout.
Timeout is initialized only before first socket send. Queued packet
may be triggered later than other and may cause that same block is
allocated multiple time.
Signed-off-by: Juha Heiskanen <juha.heiskanen@nordicsemi.no>
This commit adds the MAINTAINERS entry for the Toolchain Integration,
with @tejlmand as the maintainer and @stephanosio as a collaborator.
The purpose of this is to provide a corresponding MAINTAINERS entry for
the "area: Toolchains" and differentiate the toolchain integration-
related maintenance tasks from the general build system maintenance
tasks.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Fix Broadcast ISO and Synchronized Receiver project
configurations related to IPC use.
Relates to commit cf6a58d3f6 ("bluetooth: hci: rpmsg:
use ipc service library").
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
This change is controlling of function parameters before
configuring the STM32_DMA_HAL_OVERRIDE mode.
Then, in case the DMA channel is not valid (wrong ID) or busy,
an error occurs before overriding the DMA channel.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixing a bug where get_regs() was being executed before MMIO mapping
moving the declaration of reg_base after DEVICE_MMIO_MAP
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
